Intel MCS 51 User Manual page 241

in~o
87C51GB HARDWARE DESCRIPTION
CCAPnHcan containany integerfrom Oto 255to vary
the duty cyclefrom a 100%to 0.4%. A
0%0
duty cycle
can be obtainedby writing directlyto the port pin with
the CLRbit instruction.To calculatethe CCAPnHval-
ue for a givenduty cycle, w the followingequation:
CCAPnH = 256x (1 - Duty Cycle)
where CCAPUHis an 8-bit integer and Duty Cycleis
expressedas a fraction. See Figure 24.
8.0 SERIALPORT
The serial port is full duple~ meaningit can transmit
and receivesimultaneously.lt is also receive-buffered,
meaningit can commencereception of a second byte
before a previouslyreceived byte has been read horn
the receive register. (However, if the first byte still
hasn't been read by the time reception of the second
byte is complete,one of the bytes will be lost).
The serial port receive and transmit registers are both
accessedthroughSpecialFunction RegisterSBUF.Ac-
tually, SBUFis two separate registera,a transmit but%r
and a receivebuffer.Writing to SBUFloads the trans-
mit register, and reading SBUF accessesa physically
separate receiveregister.
The serialport cantrol and status registeris the Special
FunctionRegisterSCK)N cable 17).This registercxm-
tains the modeselectionbits (SMOand SM1);the SM2
bit for the multiprocess o r modes; the ReceiveEnable
bit (REN); the 9th data bit for transmit and receive
(TB8 and RB8); and the serial port interrupt bits (T1
and RI).
Din-f CYCLE
CCAPnH
OUTPUT WAVEFORM
100% 00
90%
50%
128 ~
10%
0.4%
255 ~
270697-26
Figure24.CCAPnH VeriesDutyCycle
6-33