High Speed Output Mode; Watchdog Tmer Mode - Intel MCS 51 User Manual

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8XC51FXHARDWARE DESCRIPTION
During the interrupt routine, a new 16-bitcompare vaf-
regularhold-off signals to the Watchdog. These
circtits
ue canbe written to the compareregisters (CCAPnH
are used in applications that are subject to electrical
and CCAPnL). Notice, however, that a wn"te to noisq power glitches, electrostatic diseharg% etc., or
CCAPnL clears the ECOMn bit which temparily dir- where high reliability is required.
ables the companstorjimction while these registens are
being updated so an invalid match does not occur. A
The Watchdog Timer function is only available on
write to CCAPnH sets the ECOMn bit and re-ena bles PCA module 4. In this mode, every time the count in
the comparator. For this reason, user software should the PCA timer matchea the value stored in module 4's
write to CCAPnL first, then CCAPnH. compare registers, an internal reset is generated. (See
Figure 19.) The bit that selects this mode is WDTE in
the CMOD register. Module 4 must be setup in either
6.5
High Speed Output Mode
comparemode as a SoftwareTimer or High Speed Out-
put.
The High Speed Output (HSO) mcde toggles a CEXn
pin when a match occurs between the PCA timer and a
When the PCA Watchdog Timer timeaout, it resets the
pm-loaded value in a module's compare registers. For
chip just like a hardware re@ except that it doea not
this mode, the TOGn bit needs to be set in addition to
drive the reset pin high.
the ECOMn and MATn bits as seen in Figure 18. By
setting or clearing the pin in software, the user can
To hold off the reset, the user has three options:
select whether the CEXn pin will change from a logical
O to a logicaf 1 or vice versa. The user rdso b the
(1) periodically change the compare value so it will
option of flagging an interrupt when a match event oc-
never match the PCA timer,
curs by setting the ECCFn bit.
(2) periodically change the PCA timer vafue so it will
never match the compare value,
The HSO mode is more accurate than toggling port
(3) disable the Watchdog by clearing the WDTE bit
pins in software because the toggle occurs before
before a match occurs and therrfater re-ena ble it.
branching to an interrupt. That iy interrupt latency
will not effect the accuracy of the output. If the user
The first two options are more refiable because the
does not change the compare registers in an interrupt
Watchdog Timer is never disabled as in option #3. The
routin~ the next toggle will occur when the PCA timer
second option is not recommended if other PCA mod-
rolls over and matches the last compare value.
ules are being used since this timer is the time base for
all five modules. Thus in most applications the first
solution is the best option.
6.6 Watchdoa Timer Mode
If
a
Watchdog Timer is not needed, modufe 4 can still
A Watchdog Timer is a circuit that automatically in-
be used in other modes.
vokea a reset unless the system being watched sends
PT
PCA
l'ws/cou
PIN
270S5S-15
Figure 18. PCA 18-Bit Comparator Mode: Software Timer and High Bpeed Output
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