Glossary - Intel MCS 51 User Manual

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83C152 HARDWARE DESCRIPTION
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GLOSSARY
ADR0,1,2,3 (95H, OA5H, OB5H,OC5H) - Address
Match Registers 0,1,2,3- The contents of these SFRS
are comparedagainst the address bits from the serial
data on the GSC. If the address matchesthe SFR, then
the C152 accepts that frame. If in 8 bit addreaaing
mode,a match with artyof the four registerswilltrigger
acceptance.In
16
bit
addressing
mode, a match with
ADR1:ADROor ADR3:ADR2 will be accepted. Ad-
dress lengthis determinedby GMOD (AL).
AE - AlignmentError, see RSTAT.
AL -
Address
L ength, see
GMOD.
AMSKO,l(OD5H,OE5H)- AddressMatch Mssk 0,1-
I&ntifies which bits in ADRO,l are "don't care" bits.
Setting a bit to 1 in AMSKO,l identifies the corre-
spondingbit in ADDRO, I as not to be examinedwhen
comparingaddresses.
BAUD - (941-1) C ontains the programmablevalue for
the baudrate generatorfor the GSC.The baud rate will
equal (fose)/((BAUD+ 1) X 8).
BCRLO,l(OE2H,OF2H)- Byte Count Register Low
0,1- Containsthe lower byte of the byte count. Used
during DMA transfers to identify to the DMA chan-
nels whenthe transfer is complete.
BCRHO,l(OE3H,OF3H)- Byte Count Register High
0,1- contains the upper byte of the byte count.
BKOFF(OC4H)- BackoffTimer - The baokofftimer is
an eightbit count-downtimer with a clockperiodequal
to one slot time. The backoff time is used in the
CSMA/CDcollisionreardutionalgorithm.
BOF - Beginningof Frame flag - A term commonly
used when dealing with paoketized&ta. Signifiesthe
beginningof a frame.
CRC - CyclicRedundancyCheck - An error checking
routinethat mathematicallymanipulatesa valuedepen-
dent on the incomingdata. The purpme is to identify
whena frame haa been receivedin error.
CRCE- CRC
Error, see
RSTAT.
CSMA/CD - Stands for Carrier sen% Multiple Ac-
cess,with CollisionDetection.
CT - CRC Type, see GMOD.
DARLO/1(OC2H,OD2H)- DestinationAddressReg-
ister Low0/1 - Containsthe lowerbyte of the destina-
tions'addreaswhen performingDMA trsnsfers.
DARHO/1(OC3H,OD3H)- DestinationAddressReg-
ister Low0/1 - Containsthe upper byte of the destina-
tions'addrcaswhen performingDMA
transfers.
DAS - DestinationAddress Space,see DCON.
DCJ - D.C. Jam, see MYSLOT.
DCGNO/1(092H,093H)
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I DAS I IDA ! SAS I ISA I DM ! TM I DONE I Go I
The DCON registerscontrolthe operationof the DMA
chasmelsby dete rminingthe source of data to be trans-
ferred,the destinationofthe data to be transfer, and the
variousmodeaof operation.
DCON.O(00) - EnableaDMA Transfer - When set it
enables a DMA channel. If block mode is set then
DMA transfer starts as soon as possibleunder CPU
control. If d emrmd mode is set then DMA transfer
starts whena demandis asserted and recognized.
DCON.1 (DONE) - DMA Transfer is Complete -
When set the DMA transfer is complete.It is set when
BCR equals O and is automatically reset when the
DMA vectors to its interrupt routine. If DMA inter-
rupt is disabledand the user software executesa jump
on the DONE bit then the user software must also
reset the done bit. If DONE is not set, then the DMA
transfer is not complete.
DCON.2 (TM) - Transfer Mode - When set, DMA
burst transfers are used if the DMA channel is config-
ured in block mode or external interrupts are used to
initiate a transfer if in Demand Mode. When TM is
clear~ Alternate CycleTransfers are used if DMA is
in the BlockMode,or LocalSerialcharmel/GSCinter-
rupts are used to initiate a transfer ifin DemandMode.
DCON.3 (DW - DMA channel Mode - When set,
Demand Mode is used and when cleared, BlockMode
is used.
DCON.4 (ISA) - Increment Source Address - When
m the sourceaddressregistersare automaticallyincre-
mented during each transfer. When cleared, the source
address registersare not incremented.
DCON.5 (SAS) -
SourceAddressSpace- WhenW6the
source of data for the DMA transfers is internal data
memoryifautoincrementis also set. Ifautoincrernentis
not set but SASis, then the source for data will be one
of the SpecialFunctionRegisters.WhenSASis cleared,
the source for data is external data memory.
DCON.6 (IDA) - Increment Destination Address
Space - When set, destinationaddress registemare in-
cremented once after each byte is transferred. Where
cleared, the destinationaddress registers are not auto-
maticallyincremented.
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