Interruptstructure - Intel MCS 51 User Manual

inl#
83C152 HARDWARE DESCRIPTION
GO is the enablebit for the DMA Channel itself. The
DMA Channelis inactiveif GO = O.
PCON SMOD I ARE I REQ ] GAREN I XRCLK I GFIEN I PDN I IDL
ARB
enables the
DMA logicto detect ~ and gener-
ate HLDA. After it has activatedHLDA, the C152will
not begina new DMA to or from External Data Mem-
ory as long as ~ is seen to be active. This logicis
disabledwhenARB = O,and enabledwhenARB = 1.
REQ enablesthe DMA logicto generate~ and de-
tect HLDA before performinga DMA to or from Ex-
ternal Data Memory.After it has activated ~, the
C152willnot beginthe DMA until= is seento be
active. This logicis disabledwhen REQ = O,and en-
abled when REQ = 1.
5.0
INTERRUPTSTRUCTURE
The 8XC152
retains all fiveinterruptaof the 80C51BH.
Sixnewinterrupts are addedin the 8XC152,to support
its GSC and the DMA features. They are as listed be-
low,and the flagsthat generatethem are shownin Fig-
ure 5.1.
GSCRV — GSC ReceiveValid
GSCRE — GSC ReceiveError
GSCTV — GSC TransmI " tValid
GSCTE — GSC Transmit Error
DMAO — DMA Chanmel O Done
DMA1 — DMA Channel 1 Done
As shownin Figure5.1,the ReceiveValid interrupt ean
be signated either by the RFNE tlag (Receive FIFO
Not Empty), or by the RDN flag (Receive Done).
Which one of these flags causes tie interrupt depends
on the setting of the DMA bit in the SFR named
TSTAT.
DMA = O means the DMA hardware k not config-
ured to servicethe GSC, so the CPU will serviceit in
software in response to the Receive FIFO not being
empty-In that case,RFNE generatesthe ReceiveValid
interrupt.
DMA = 1 meansthe DMA hardware is configuredto
service the GSC, in which case the CPU need not be
interrupted till the receive is complete. In that case,
RDN generatesthe ReceiveValid interrupt.
Sknkrly the T ransmit Valid interrupt ean be signaled
either by the TFNF flag (Transmit FIFO Not Full), or
by the TDN flag (Transmi t Done), depending on
whether the DMA bit is Oor 1.
Note that setting the DMA bit does not itaelf~figure
the DMA channels to seMee the GSC. That job must
be done by software writes to the DMA registers. The
DMA bit only seleots whether the GSCRV and
GSCTVinterrupts are flaggedby a FIFO needingserv-
ice or by an "operationdone" signal.
The Receive and Transmi t Error interrupt flags are
generatedby the logicalOR of a numberof error condi-
tions, which are describedin Section3.6.5.
Each interrupt is assigneda freed location in Program
Memory,and the interrupt causes the CPU to jump to
that location. All the interrupt fiags are sampled at
S5P2of everymachine CYCIG a nd then the samples are
sequentiallypolled during the next machine cycle. If
more than one interrupt of the same priority is activq
the one that is highest in the polling sequenceis serv-
iced first. The interrupts and their fixed locations in
Program Memoryare listedbelowin the order of their
pollingsequence.
270427-42
2EP--CRE
270427-44
7FNF '1 DMA= ~
$%+.s.
~N
d
MA.
1
270427-45
IaED-'"m
270427-46
OONE
~ OMAO
(OCONO.1)
270427-47
'NE ~DMAl
(OCON1.1)
270427-4S
Figure 5.1. Six New Interrupts in the 8XC152
7-60