Intel MCS 51 User Manual page 250

i~.
87C51GB HARDWARE DESCRIPTION
Table21.EXICON: E xternalInterruptControlRegister
EXICON
Bit
EXICON
Symbol
—
IE6
IE5
IE4
IE3
IE2
IT3
IT2
ResetValue= XOOO O OOOB
Address = O(%H
NotBitAddressable
7 6 5 4 3 2 1 0
—
IE6 IE5 IE4 IE3 IE2 IT3 IT2
Function
Notimplemented, reserved forfuture use.*
interrupt 6 Edge ffag.Thisbitissetbyhardware w henanexternal interrupt edge
isdetected.
Interrupt 5 Edge flag.Thisbitissetbyhardware w henanexternal interrupt edge
isdetected.
interrupt 4 Edgeflag.Thisbitissetbyhardware w henanexternal interrupt edge
isdetected.
Interrupt 3 Edge flag.Thisbitissetbyhardware w henanerrternal interrupt edge
isdetected.
Interrupt 2 Edge flag.Thisbitissetbyhardware w henanexternal interrupt edge
isdetected.
Interrupt 3 Typecontrol b it.Thisbitissetorcleared bysoftware t ocontrol
whether I NT3ispositive o rnegative t ransition a ctivated. WhenIT3ishigh, I E3is
setbya positive t ransition o npinINT3.WhenIT3islow,IE3issetbya negative
transition onpinINT3.
Interrupt 2 Typecontrol bit.Thisbitissetorcleared bysoftware t ocontrol
wheth& lNT2iapositive o rnegative t ransition a ctivated. WhenIT2ishigh, I E2is
setbya positive t ransition o npinINT2.WhenIT2islow,IE2issetbya negative
transition onpinINT2.
"Using s oftware should n ot w rite Is toreserved bits. T haae bits may beusad infuture S 051 family P roducts toinvoke
I
new
f&tures.
Inthatcase, thereset o rinactive value ofthenew btiwill b eO,anditsactive v alue-will be1,Thevalue
read from resewed btiisindeterminate.
The flags thatactually generatethe interrupts are bits
IEOand IE1 in TCON and IQ IE3, IE4, IE5, and IE6
in EXICON.These flagsare clearedby hardwarewhen
the service routine is vectoredto if the interrupt was
transition-activated.If the interruptwas level-activated,
then the external requestingsourceis what controlsthe
requestflag, rather than the on-chiphardware. The ex-
ternrd interrupts are enabled through bits EXO and
EXl in the IE register and EX2,EX3, EX4, EX5, and
EX6 in the IEA register.
Sincethe external interrupt pinsare sampledonce each
machinecycle an input highor low shouldhold for at
least 12 oscillator periods to ensure sampling. If the
extemsl interrupt is transition-activata the external
sourcehas to hold the request pin high for at least one
cycle, and then hold it low for at least one cycle to
ensure that the transition is seen so that interrupt re-
quest flag IEx will be set. IEx will be automatically
clearedby the CPU when the serviceroutine is called.
If external interrupt INTOor ~ is level-activated,
the external source has to hold the request active until
the requested interrupt is actually generated. Then it
has to deactivate the request beforethe interrupt serv-
ice routine is completed,or elseanother interrupt will
be generated.
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