Intel MCS 51 User Manual page 225

in~.
87C51GB HARDWARE DESCRIPTION
timer function (counting machine cycles) and takes
over the use of TRl and TFl from Timer 1.Thus THO
nowcontrolsthe Timer 1interrupt. The logicfor Mode
3 on Timer Ois shownin Figure 11.
Mode 3 is providedfor applicationsrequiringan extra
8-bit timer or counter. When Timer O is in Mode 3,
Timer 1 can be turned on and offby switchingit out of
and into its own Mode 3, or can still lx used by the
serial port as a baud rate generator, or in any applica-
tion not reqtig an interrupt.
5.2
Timer 2
Timer 2 is a 16-bitTimer/Counter which can operate
either as a diner or as an eventcounter.This is selected
by bit C—T2in the SFR T2CON(Table 7). It has the
followingthree operating modes:
Timer 2 Capture,
Timer 2 Auto-Reload(up or down counting),and
Timer 2 as a Baud Rate Oenerstor.
The modes are also selected by bits in T2CON as
shownin Table 6.
TableI
ICLK+ ICLif
o
0
1
x
x
rimer 2
:P/m
o
1
x
o
x
Present only onthe87C51 FC
)peral
r2"oE
o
0
x
1
x
1
1
1
1
0
dea
Mode
16-Bit
Auto-Reload
l&Bit
Capture
Baud-Rate
Generator
Clock-out
onPI.0*
Timer O ff
Table7.T2CON: T imer/Counter 2 ControlRegister
T200N Address = OC6H Reaet V alue= 0000OOOOB
BitAddressable
I
TF2
EXF2 RCLKI TCLK I EXEN2 TR2
Clz cP/m
Bit 7
6 5
4
3 2
1 0
8ymbol Function
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
cm
cP/RD
Timer 2 overflow flagsetbya Timer 2 overflow andmust b ecleared bysoftware. TF2willnot
besetwheneither RCLK= 1orTCLK= 1.
Timer 2 external flagsetwhen either a capture orreload iscaused bya negative t ransition o n
T2EXandEXEN2= 1.When Timer2interrupt isenabled EXF2= 1willcause theCPUto
vector t otheTimer 2 interrupt routine. EXF2must b ecleared bysoflware. EXF2doeanot
cause aninterrupt inup/down counter m ode (DOEN= 1).
Receive clock flag.When set, causes theserial p orttouseTimer 2 overflow pulses forits
receive clock inserial p ortModes 1 and3. RCLK= Ocauses Timer1overflow tobeused for
thereceive clock.
Transmit clock flag.Whenset,causes theserial p ortto useTimer 2 overflow pulses forits
transmit clockinserial p ortModes 1and3.TCLK= Ocauses Timer1 overflows to beused
forthetransmit clock.
Timer 2 external enable flag.Whenset allows a capture orreload tooccur a sa result o fa
negative t ransition o nT2EXifTimer 2 isnotbeing used toclock theserial p ort.EXEN2= O
causes Timer
2
toignore eventa atT2EX.
Start/stop
oontrol for Timer 2. A logic 1 starts the timer.
Timer or counter select, (Timer 2)
O = Internal timer (OSC/12 or OSC/2 in baud rate generator mode.)
1 = External event counter (falling edge triggered).
Capture/Reload flag. When set, captures will occur on negative transition at T2EX if EXEN2
= 1. When cleared, auto-reloads will
occur e ither withTimer2 overflows ornegative
transitions atT2EXwhenEXEN2= 1.When either RCLK= 1 orTCLK= 1,&is bitis
ignored andthetimerisforced toauto-reload on17mer2 overflow.
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