Intel MCS 51 User Manual page 269

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83C152 HARDWARE DESCRIPTION
2.1.1 SPECIAL FUNCTION REGISTERS (SFRS)
The following
list contains all the SW their names
and function. All of the SFRSof the 80C51BHare re-
tained and for a detailedexplanationof their operation,
please refer to the chapter, "Hardware Descriptionof
the 8051 and 8052" that is found in the Embedded
ControllerHandbook.An overviewof the new SFRSis
foundin Section2.1.1.1,with a detailedexplanationin
Section3.7, Section4.5, and 6.0.
2.1.1.1 New SFRS
The followingdescriptionsare quick overviewsof the
new SFRS,and not intended to givea completeunder-
standing of their use. The reader should refer to the
detailed explanation in Section 3 for the GSC SFRS,
and Section4 for the DMA SFRS.
ADR 0,1,2,3- (95H, OA5H,OB5H,OC5H)Contains
the four bytes for address matchingduringGSCopera-
tion.
AMSKO- (OD5H)selects "don't care" bits to be used
with ADRO.
AMSK1 - (OE5H)Selects"don't care" bits to be used
with ADR1.
BAUD - (W-I) Contains the prograrnma b le value for
the baud rate generatorfor the GSC.The baudrate will
equal (foac)/((BAW+ 1) X 8).
BCRLO- (OE2H)Contains the low byte of a comrt-
down counter that determines when the DMA access
for Channel Ois complete.
BCRHO- (OE3H)Contains the high byte for count-
downcounter for ChannelO.
BCRL1 - (OF2H)Same as BCRLOexcept for DMA
Channel L
BCRH1 - (OF3H)Same as BCRHOexcept for DMA
Channel 1.
BKOFF - (OC4H)An 8-bit count-downtimer used
with the CSMA/CD resolutionatgorithm.
DARLO- (OC2H) Containsthe lowbyte of the destina-
tion address for DMA Channel0,
DARHO- (OC3H)Containsthe highbyte of the desti-
nation address for DMA channel O.
DARL1 - (OD2H)Same as DARLOexcept for DMA
Channel 1.
DARH1 - (OD3H)Same as DARHOexceptfor DMA
Channel 1.
DCONO - (92H) Contains the Destination Address
Space bit (DAS), Increment Destination Address bit
(IDA), Source Addreas Space bit (SAS), Increment
Source Address bit (ISA), DMA Channel Mode bit
(DM), Transfer Mode bit (TM), DMA Done bit
(DONE), and the 00 bit (GO). DCONOis used to
control DMA ChannelO.
DCONI - (93H) Same as DCONOexcept this is for
DMA Channel 1.
GMOD - (84H) Contains the Protocol bit (PR), the
Preamble Mgth (PL1,O),CRC Type (CT), Addf-
Lersgth(AL),Mode select (M1,O), a nd ExternalTrans-
mit Clock(TXc). This register is used for GSC opera-
tion only.
IENI - (OC8H) Interrupt enableregister for DMA and
GSC illtt31111ptS.
IFS - (OA4H) Determinesthe numberof bit times sepa-
rating transmittedframes.
IPN1 - (OF8H)Interrupt priority register for DMA
and GSC interrupts.
MYSLOT- (OF5H)Contains the Jamming mode bit
(DC.7),the Determini s tic Collision Resolution Algo-
rithm bit (DCR), and the DCR slot address for the
GSC.
P4 - (oCOII)COntainsthe memory"image" of Port 4.
PRBS - (OE4H)Contains a pseudo-randomnumber to
be usedin CSMA/CDbackoffalgorithms.Maybe read
or written to by user software.
RFIFO - (F4H)RFIFO is usedto accessa 3-byteFIFO
that containsthe receivedata from the GSC.
RSTAT - (OE8H)Contsins the Hardware Based Ac-
knowledgeEnable bit (HABEN), Global ReceiveEn-
able bit (GREN), Receive FIFO Not Empty bit
=), Receive Done bit (RDN), CRC Error bit
(CRCE), Alignment Error bit (AE), Receiver Colli-
sion/Abort detect bit (RCABT), and the overrun bit
(OVR),used with both DMA and GSC.
SARLO- (OA2H)Contains the low byte of the source
address for DMA transfers.
SARHO- (OA3H)Gmtsins the high byte of the source
address for DMA transfers.
SARL1- (OB2H) S ameas SARLObut for DMA Chan-
nel 1.
SARH1- (oB3H)Sameas SARH1but for DMA Chan-
nel 1.
SLOTTM- (OB4H)Determines the length of the slot
time in CSMA/CD.
TCDCNT - (OD4H)Contains the numberof collisions
in the current frame if using CSMA/CD GSC.
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