Intel MCS 51 User Manual page 235

intel.
87C51GB HARDWARE DESCRIPTION
Each module has a mode register called CCAPMn
(n = O, 1, 2, 3, or 4) to select which function it will
7.3 PCACaptureMode
perform. The ECCFn bit enables the PCA interrupt
Bothpositiveand negativetransitionsoentriggera cap-
when a module's event flag is set. The event tlags
ture withthe PCA. This givesthe PCA the flexibilityto
(CCFn) are located in the CCON register and get set
measure periods,pulse widths, duty cycles+ and phase
when a capture event, software timer, or high speed
differenceson up to five separate inputs. Setting the
output eventoccurs for a givenmodule.
CAPPn snd/or CAPNn bits in the CCAPMn mode
Each mcdule also has a pair of 8-bit compare/capture
register ('fable 14) selects the input trigger-positive
end/or negativetransition-for modulen. Refer to Fig-
registers (CCAPnH and CCAPnL) associatedwith it.
m 19.
These registersstore the time whena capture event oc-
curred or whena compare
event
shouldoccur. For the
Table 15 shows the combinations of bits in the
PWM mode,the high byte register CCAPnH controls
CCAPMn register that are valid and have a defined
the duty cycleof the waveform.
function.Invalid combinationswill produce undetined
results.
Table14.CCAPMn: P CAModules Compare/Capture R egisters
CCAPMn Address CCAPMOODAH
ResetValue= XOOO O OOOB
(n = O-4) CCAPM1 ODBH
CCAPM2 ODCH
CCAPM3 ODDH
CCAPM4 ODEH
NotBitAddressable
I
—
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Bit 7 6 5 4 3 2
1 0
SymbolFunction
—
Notimplemented, reserved f orfuture use*.
ECOMnEnable Comparator. ECOMn= 1 enables thecomparator function.
CAPPn capture Positive, CAPPn = 1 enables positive e dgecapture.
CAPNn Capture Negative, CAPNn = 1 enables negative e dgecapture.
MATn Match. W henMATn= 1,a match ofthePCAcounterwith thismodule'a c ompare/cspture
register c auses theCCFnbitinCCONto bsset,flagging a ninterrupt.
TOGn Toggle. W henTOGn= 1,a match ofthePCAcounterwith thismodule's c ompare/cspture
register c auses theCEXn pintotoggle.
PWMn Pulse WidthModulation Mode. P WMn= 1 enables theCEXn pintobeused asa pulse width
modulated o utput.
ECCFn Enable CCFinterrupt. Ensblescompare/capture flagCCFn intheCCONregister togenerate
aninterrupt.
NOTE
User software should not write 1s to resarved
bite.
These bite
maybe used in future 8051 family products to invoke
new features. In that ceae,the reset or inactive value of the new bit will be O, and its aofive value will be 1. The value
read from a reasrvsd bit is indsterrninate.
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