Intel MCS 51 User Manual page 289

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83C152 HARDWARE DESCRIPTION
Jam
The jam signalis generated by any 8XC152 that is in-
volvedin transmittinga frame at the time a collisionis
detectedat its GRXD pin. This is to ensure that if one
transmittingstation detectsa collision,all the other sta-
tions on the networkwill also detect a collision.
Ifa transmitting8XC152detects a collisionduringthe
prearnble/BOF part of the fkame that it is trying to
transmit, it will completethe preamble/BOF and then
begin the jam signal in the fmt bit time after BOF. If
the collisionis detected later in the frame, the jam sig-
nal willbeginin the next bit time after the collisionwas
detected.
Thejam signallasts for the samenumberof bit timesas
the selectedCRC length-either 16-or 32-bittimes.
The 8XC152provideatwo typeaofjam signalsthat can
be selectedby user software.If the node is DC-coupled
to the networlqthe DCjam can be selected.In this case
the GTXD pin is pulled to a logicOfor the durationof
the jam. If the nodeis AC-coupledto the networlqthen
AC jam must be selected. In this case the GSC takes
the CRC it has calculatedthus far in the transmission,
inverts each bit, and transmits the inverted CRC. The
selectionof DC or AC jam is made by setting or clear-
ing the DCJ bit, which resides in the SFR named
MYSLOT.
When the jam signal is completed, the 8XC152goes
into an idle state. Preamneably,other stations on the
networkare also generatingtheir ownjam signals,after
whichthey too go into an idle state. When the 8XC152
detects the idle state at its ownGRXD pin, the backoff
sequencebegins.
Backoff
There are threesoftware
selectablecollisionresolution
algorithms in the 8XC152.The selection is made by
writingvaluesto 3 bits:
DCR Ml MO Algorithm
o 0 0
Normal Random
o
1 1
Alternate Random
1
1
1 Deterministic
Ml and MO rside in GMOD, and DCR is in
MYSLOT.
In the Normal Random algorithm, the GSC backs off
for a random number of slot times and then decides
whether to restart the transmission.The baekofftime
beginsas soonas a line idle conditionis detected.
The Alternate Random algorithm is the same as the
Normal Random except the backofftime doesn'tstart
until an IFS has
trStlS@d.
In the Deternums
" "tic algorithm, the GSC backs off to
await its predetermined turn.
Random Backoff
In either of the random algorithms,the first thing that
happens after a collision is detected is that a 1 geta
shifted into the TCDCNT (Transmit Cdliaion Detect
Count) register, from the right.
Thus if the software cleared TCDCNT before telling
the GSC to transmit, then TCDCNT keeps track of
how many times the transmission had to be aborted
because of collisions:
TCDCNT = ~ first attempt
OMOOOOl first collision
OOOOQO1l second collision
mill third collision
Oooo1111 fourth collision
. . . . . . . . . . . . .
11111111
eighth collision
After TCDCNT gets a 1 shifted into it, the logical
AND of TCDCNT and PRBS is loaded into a count-
down timer named BKOFF. PRBS is the name of an
SFR which contains the output of a pseudo-random
binary sequencegenerator. Its function is to providea
random number for usc in the backoffalgorithm.
Thus on the first collisionBKOFF gets loadedrandom-
ly with either OM030Ml or OOWO@31. If there is a sec-
ond collisionit getsloadedwith the randomselectionof
OOOWOOO, ~1, @XXOOIO, or OtMOOO1l. On the
third collisionthere willbe a randomselectionamong8
possiblenumbers.On the fourth, among 16,tic. Figure
3.5showsthe logicalarrangementof PRBS,TCDCNT,
and BKOFF.
BKOFF starts counting down from its prebad value,
counting slot times. At any time, the current value in
BKOFF can be read by the CPU, but CPU writes to
BKOFF have no effect. While BKOFF is counting
down, if its current value is not O,transmissionis dis-
abled. The output signal "BKOFF = O" is asserted
whenBKOFF reachesO,and is used to re-enabletrans-
mission.
At that time tranrim ission cart proceed, subject of
course to IFS enforcement,unless:
shiftinga 1 into TCDCNT from the right caused a 1
to shift out from the MSBof TCDCNT, or
. the collisionwas detected after TFIFO had been ac-
cessedby the transmit hardware.
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