Assigning Higher Priority To One Or More Interrupts; Priority Within Level; Bit Addressable - Intel MCS 51 User Manual

M=@-51 PROGRAMMER'SGUIDE AND INSTRUCTION SET
ASSIGNING HIGHER PRIORITY TO ONE OR MORE INTERRUPTS:
In order to assign higher priority to an interrupt the correspondingbit in the 1Pregister must be set to 1.
Rememberthat whilean interrupt servieeis in progress,it cannot be interrupted by a lower or same levelinterrupt.
PRIORITV WITHIN LEVEL:
Priority within level is only to resolvesimultaneousrequestsof the same priority level.
From high to low, interrupt sourcesare listed below:
IEO
TFo
IE1
TF1
RI or TI
TF2 or EXF2
1P:INTERRUPT PRIORITY REGISTER. BIT ADDRESSABLE.
If the bit is O,the correspondinginterrupt has a lowerpriority and if the bit is 1 the correspondinginterrupt has a
higher priority.
I
— —
PT2
Ps PTl
Pxl PTO Pxo
—
1P.7
—
1P.6
PT2 1P. 5
Ps 1P.4
Pm 1P. 3
Pxl 1P.2
PTo
1P. 1
Pxo 1P.O
Not irnplementi reservedfor future use.*
Not implemented,reservedfor future use.*
Detines the Timer 2 interrupt priority level(8052only).
Definesthe SerialPort interrupt priority level.
Definesthe Timer 1 interrupt priority level.
Defines External Interrupt 1 priority lexwl.
Defines the Timer Ointerrupt priority level.
Definesthe External Interrupt Opriority level.
*Usersoftware should not write 1s to reserved bits. Theaebits may be used in fiture MCS-51products to invoke
new features. In that case, the reset or inactive valueof the new bit will be O,and its active value willbe 1.
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