Intel MCS 51 User Manual page 309

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83C152 HARDWARE DESCRIPTION
GMOD.7~CLK)
- ExternalT ransmit Clock- If set
an external 1X clock is used for the transmitter. If
cleared the internal baud rate generator provides the
transmit clock. The input clock is applied to P1.3
~~).
The
user software is responsible
for setting or
clearing this flag. External receiveclock is enabled by
setting PCON.3.
IFS (OA4H)- Interframe Spacing - Determm " es the
number of bit times separating transmitted frames in
CSMA/CD and SDLC. A bit time is equal to l/baud
rate. Only even interfkarnespace periodscan be used.
The numberwritten into this registeris dividedby two
and loadedin the moat significantsevenbits. Complete
interfkamespace is obtainedby counting
this seven
bit
number down to zero twice. A user software read of
this registerwill givea vafuewherethe sevenmost sig-
nificantbits givesthe current count valueand the least
significantbit showsa one for the first countdown and
a zero for the secondcount. The valueread may not be
vafidas the timm is clockedin periodsnot necessarily
associatedwith the CPU read of IFS. Loadingthis reg-
ister with zero results in 256bit times.
MYSLOT(OF5H)- Slot AddreasRegister
76543210
DcJ DCR SA5 SA4 SA3 SA2 SA1 SAO
I SAn = SLOT ADDRESS (BITS 5 – O)
Figure 3.15. MYSLOT
MYSLOT.0,1, 2, 3, 4, 5- Slot Address- The six ad-
dress bits choose1 of 64 slot addreases.Address63 has
the highest priority and address 1 has the lowest. A
value of zero wilf prevent a station from transmitting
during the collisionresolutionperiod by waiting until
all the possibleslot timea have efapsed.The user soft-
ware normallyinitializeathis address in the operating
software.
MYSLOT.6(DCR) - Deterministic CollisionResolu-
tion Algorithm- When aeLthe alternate collisionreso-
lution algorithmis selected.Retriggeringof the IFS on
reappearanceof the carrier is alsodisabled.When using
this feature Alternate BaekoffMode must be selected
and several other registers must be initialized. User
softwaremust initialize
TCDCNT
with the maximum
numba of slots that are most approptite for a particu-
lar application.The PRBS register must be set to all
onea.Thisdisablesthe PRBSby freezingit's
eorttents at
OFFH. The backoff
timer is used to count down the
numberofslotsbased on the slot timer valuesettingthe
period of one slot. The user softwareis responsiblefor
setting or clearingthis flag.
MYSLOT.7(DCJ) - D-C. Jam - Whenset selectaD.C.
type ~, when
cl-,
selectsA.C. type jam. The user
softwareis responsiblefor settingor clearing
this flag.
PCON (087H)
7654
3 210
SMOD ARB REQ GAREN XRCLK GFIEN PD IDL
PCON contains bits for power control, LSC control,
DMA control, and GSC control. The bits used for the
GSC are PCON.2, PCON.3, and PCON.4.
PCON.2 (GFIEN) - GSC Flag Idle Enable - Setting
GFIEN to a 1caused idle flagsto be generatedbetweem
transmitted frames in SDLC mode. SDLC idle tlags
consist of 01111110 tlags creating the sequence
01111110011111110 . .....011111110. A possibleside
effectof enablingGFIEN is that the maxim um possible
latency from writing to TFIFO until the first bit is
transmitted increased from approximately2 bit-times
to around 8 bit-times. GFIEN has no effect with
CSMA/CD.
PCON.3(XRCLK) - GSC ExternalReceiveClockEn-
able - Writinga 1 to XRCLK enablesan external clock
to be applied to pin 5 (Port 1.4).The external clock is
used to determine when bits are loadedinto the receiv-
er.
PCON.4(GAREN) - GSC AuxilimyRemiver Enable
Bit - This bit needsto be set to a 1 to enablethe recep-
tion of back-to-back SDLC frames. A back-to-back
SDLC frame is when the EOF and BOF is shared te-
tweentwo sequentialframes intendedfor the same sta-
tion on the link. If GAREN containsa Othen the re-
ceiverwill be disabled upon receptionof the EOF and
by the time user software re-enablesthe receiver the
first bit(s) may have already passed,in the case of back-
to-back frames Setting GAREN to a 1, prevents the
receiver from being disabled by the EOF but GREN
wilfbe cleared and can be checkedby user softwareto
determinethat an EOF has beur received.GAREN has
no effectif the GSC is in CSMA/CD mode.
PRBS (OE41-1) - Paeudo-RandomBinary Sequence -
This register contains a pseudo-randomnumber to be
usedin the C3MA/CD backoffalgorithm.The number
is generated by using a feedbackshift register clocked
by the CPU phaseclocks. Writingatl onesto the PRBS
willfreezethe value at all ones.Writingany other value
to it will restart the PRBS generator.The PRBS is ini-
tialized to all zero'sduring RESET.A read of location
OE4Hwill not necesard "y give the seed used in the
baekoff algorithm because the PRBS counters are
clockedby internal CPU phase clocks.This means the
eontents of the PRBS may have been altered between
the time when the seed was generated and before a
~READ has been internally executed.
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