Boolean Instructions; External Ram; Lookup Tables - Intel MCS 51 User Manual

M~@.51 ARCHITECTURAL OVERVIEW
EXTERNAL RAM
Table 5 shows a list of the Data Transfer inatmctions
that acceas external Data Memory. Only indirect ad-
&easing can be used. The choice is whether to use a
one-byte address, @M where Ri can be either RO or
RI of the selected register bank, or a two-byte address,
@DPTR. The disadvantage to using 16-bit addresses if
only a few K
bytesof externalRAMare involved is
that
16-bit addresses use alf 8 bits of Port 2 as addreas
bus. On the other hand, S-bit addresses allow one to
address a few K bytes of RAM, as shown in Figure 5,
without having to sacrifice all of Port 2.
Alf of these instructions execute in 2 pa, with a
12 MHz clock.
Tabfe 5. A List of the MCS@-51 Data
Trsnafer Instructions that Accees
Extarnsl Data Memory Spaoe
Address
Mnemonic Operation
Execution
Width Time (*)
8 b~
MOVX A,@'Ri
Read external ~
RAM @Ri
8 bb MOVX @Ri,A
Write external
RAM @Ri
2
Read external
'6 bns 'ovx "@DpTR
RAM @DPTR
2
16 bfia
Writa exlemal
'ovx 'DmR'A RAM @DPTR
2
Note that in all external Data RAM acaases, the
Ac-
cumulator is always either the destination or source of
the data.
The read and write strobes to external RAM are acti-
vated only during the execution of a MOVX instruc-
tion. Normally these signals are inactive and in fact if
they're not going to be used at u their pins are avail-
able as extra 1/0 lines. More about that later.
LOOKUP TABLES
Table 6 shows the two instructions that are available
for reading lookup tables in Program Memory. Since
these instructions access only Program Memory, the
lookup tablea can only be read, not updated. The nme-
monic is MOVC for "move constant".
If the table access is to external Program Memory, then
the read strobe is PSEN.
Table 6. Tha MCS3'-51 Lookup
Table Read Inetmctions
I
at
(A + PC) -
1
The first MOVC instruction in Table 6 can accommo-
date a table of up to
256
entries, numbered O through
255. The
number of the desired entry is loaded into the
Accumulator, and the Data Pointer is setup to point to
beginning of the table. Then
MOVC A,@A+DPTR
copies the desired table entry into the Accumulator.
The other MOVC instruction works the same way, ex-
cept the Program Counter (PC) is used as the table
base, and the table is accewed through a subroutine.
First the number of the desired entry is loaded into the
Accumulator, and the subroutine is cslled:
MOV &ENTRY_NUMBER
CALL TABLE
The subroutine "TABLE" would look like this:
TABLE: MOVC A,@A + PC
The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
have up to 255 entries, numbered 1 through 255. Num-
ber O can not be used, because at the time the MOVC
instruction is executed, the PC contains the address of
the RET instruction. An entry numbered O would be
the RET opcode itseff.
Boolean Instructions
MCS-51 devices contain a complete Boolean (single-bit)
processor. The internal RAM contains 128 addressable
bits, and the SFR space can support up to 128 other
addressable blta. Afl of the port lines are bWaddress-
abl% and each one csn be treated as a separate single-
blt port. The instructions that access these bits are not
just conditional branches, but a complete menu of
move, aeL clear, complement, OR and AND instmc-
tions. These kinds of bit operations are not essily ob-
tained in other architectures with any amount of byte-
Oriented Sottware.
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