Vita 57.1 Fmc Lpc Connector - Xilinx SP605 Hardware User's Manual

18. VITA 57.1 FMC LPC Connector

The SP605 implements the Low Pin Count (LPC, J2) connector option of the VITA 57.1.1
FMC specification.
Note:
from the SP605 board.
The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low
Pin Count (LPC) implementation. A common 10 x 40 position (400 pin locations) connector
form factor is used for both versions. The HPC version is fully populated with 400 pins
present, and the LPC version is partially populated with 160 pins.
The 10 x 40 rows of a FMC LPC connector provides connectivity for:
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Of the above signal and clock connectivity capability, the SP605 implements the full set:
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Note:
adjustable). The 2.5V rail cannot be turned off. The SP605 VITA 57.1 FMC interfaces are compatible
with 2.5V mezzanine cards capable of supporting 2.5V VADJ.
SP605 Hardware User Guide
UG526 (v1.9) February 14, 2019
The FMC LPC J2 connector is a keyed connector oriented so that a plug-on card faces away
68 single-ended or 34 differential user defined signals
1 MGT
1 MGT clock
2 differential clocks
61 ground, 10 power connections
34 differential user-defined pairs
• 34 LA pairs
1 MGT
1 MGT clock
2 differential clocks
The SP605 board VADJ voltage for the FMC LPC connector J2 is fixed at 2.5V (non-
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