Cisco XR 12000 Command Reference Manual page 19

ASIC Driver Commands
Field
Rx SClk edge
DIP4 Error
SPI bus speed
Tx Burst size
Rx Burst size sysdb
Rx SPI state
Rx SPI sync state
Rx calendar mode
Maximum RxSPI channels
Tx SPI state
Tx SPI sync state
Tx calendar mode
Maximum Tx SPI4.2 channels
3 online insertion and removal
4 Extended Flow Control
5 security policy index
6 2-bit Diagonal Interleaved Parity
7 megahertz
OL-28456-02
Cisco IOS XR Advanced System Command Reference for the Cisco XR 12000 Router, Release 4.3.x
show controllers plim asic spa bay
Description
Indicates which edge of the receive SClk to use to
sample the Tstat bus. Selects rising or falling edge as
the active transmit SClk edge.
Total number of DIP4 errors.
Note DIP4 is a parity algorithm where a 4-bit odd
parity is computed diagonally over status
words.
7
SPI bus speed in MHz .
Committed burst size in bits for traffic transmitted on
this SPA.
Committed burst size in bits for traffic received on
this SPA.
Indicates whether receive SPI is enabled or disabled.
Indicates which parameter controls the
synchronization behavior of the RXSPI module.
Indicates which RXSPI status protocol will be used
to transmit status.
Maximum number of SPI receive channels supported
on this SPA.
Indicates whether transmit SPI is enabled or disabled.
Indicates which parameter controls the
synchronization behavior of the TXSPI module.
Indicates which TXSPI status protocol will be used
to transmit status.
Maximum number of SPI4.2 transmit channels
supported on this SPA.
11