Cisco XR 12000 Command Reference Manual page 14

show controllers plim asic ingress-channel bay
|------------------|<-- Buffer Full
|
------------------ <-- Buffer End
This table describes the significant fields shown in the display.
Table 3: show controllers plim asic ingress-channel bay Field Descriptions
Field
Ifname
SPI4.2 Channel state
Bay number
Rx SPI4.2 channel number
Internal Buffer number
Rx edram buffer start address
Rx edram buffer end address
Rx edram buffer size
Rx length buffer start address
Rx length buffer end address
Rx length buffer size
Number of calendar entries
Quantum
Buffer Almost Full Threshold
Tx Queuing ASIC port number
RxEDRAM buffer threshold settings
Cisco IOS XR Advanced System Command Reference for the Cisco XR 12000 Router, Release 4.3.x
6
(0x5780)
|
(0x63ff)
Description
Identifies the primary transmit interface.
2
Indicates if the SPI4.2 channel is provisioned.
Identifies the bay that hosts the specified SPI4.2
receive channel. Can be 0 or 1.
Identifies the SPI4.2 receive channel whose
information is displayed.
Identifies the internal buffer associated with the
SPI4.2 receive channel.
Embedded DRAM buffer start address in hexadecimal
format.
Embedded DRAM buffer end address in hexadecimal
format.
Embedded DRAM buffer size in hexadecimal format.
Receive length buffer start address in hexadecimal
format.
Receive length DRAM buffer end address in
hexadecimal format.
Receive length DRAM buffer size in hexadecimal
format.
Number of entries in the SPI4.2 calendar.
Average number of bytes in the interface queue.
An increment counter which indicates that the
transmit buffer is almost full. The "Buffer Almost
Full Threshold" is expressed in hexadecimal format.
Identifies the SPI4.2 transmit port.
Displays embedded DRAM receive buffer threshold
counter settings in hexadecimal format.
ASIC Driver Commands
OL-28456-02