Troubleshooting The Server Memory - HPE Integrity rx2800 i2 series User's & Service Manual

Diagnostic Sample IPMI Events
LEDs
Processors Type E0h, 57d:26d
BOOT_INCOMPATIBLE_SLAVE
Processor Type E0h, 56d:26d
BOOT_INCOMPATIBLE_ PAL
Processors Type E0h, 34d:26d
BOOT_CPU_FAILED
Processors Type E0h, 33d:26d
BOOT_CPU_EARLY_TEST_FAIL
Processors Type 02h, 25h:71h:80h
MISSING_FRU_DEVICE

Troubleshooting the server memory

Memory DIMM load order
For a minimally loaded server, two equal-size DIMMs must be installed in the DIMM slots. For more
information, see Memory Load Order.
Memory subsystem behaviors
The processor and the integrated memory controller provides increased reliability of DIMMs. The memory
controller built into the 9300 series processor doubles memory rank error correction from 4 bytes to 8
bytes of a 128 byte cache line, during cache line misses initiated by processor cache controllers and by
DMA operations initiated by I/O devices. This feature is called double DRAM sparing, since 2 of 72
DRAMs in any DIMM pair can fail without any loss of server performance.
Corrective action, such as DIMM/memory expander replacement, is required when a threshold is reached
for multiple double-byte errors from one or more DRAM chips in the same rank. All other causes of
memory DIMM errors are corrected by the processor and reported to the CMC and CPE error logs / SID
LED panel.
Cause Source
A logical SFW
slave
processor
(thread) is
incompatible
with logical
monarch
processor
Processor SFW
PAL
incompatible
with
processor
A processor SFW
failed
A logical SFW
processor
(thread)
failed early
self test
No physical iLO MP
processor
cores
present
Troubleshooting the server memory
Notes
Possible
seating or
failed
processor
117