Execution Pipeline - Intel PXA270 Optimization Manual

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
Figure 4-1
coprocessor. After the register file, there are four concurrent pipelines to which an instruction can
be dispatched. An instruction can be issued to a pipeline if the resource is available and there are no
unresolved data dependencies. For example, a load instruction that uses the Memory pipeline can
be issued while a multiply instruction is completing in the Multiply pipeline (assuming there are no
data hazards.)
Figure 4-1. High-Level Pipeline Organization
The performance effect of resource contention can be quantified by examining the delay taken for a
particular instruction to release the resource after starting execution. The definition of "release the
resource" in this context is that the resource can accept another instruction (note: the resource may
still be processing the previous instruction further down its internal pipeline). A delay of one clock
cycle indicates that the resource is available immediately to the next instruction. A delay greater
than one clock cycle stalls the next instruction if the same resource is required. The following
sections examine the resource-usage delays for the four pipelines, and how these map onto the
instruction set.
4.10.2.1

Execution Pipeline

An instruction can be accepted into the execution pipeline when the first stage of the pipeline is
empty. Table 4-19
instructions have a resource usage delay of one clock cycle. Therefore, the execution pipeline will
always be available to the next instruction.
Table 4-19. Resource Availability Delay for the Execution Pipeline (Sheet 1 of 2)
4-46
shows a high-level representation of the operation of the PXA27x processor
Register
File
shows the instructions that execute in the main execution pipeline. All these
Instructions
WADD
WSUB
WCMPEQ
WCMPGT
WAND
WANDN
WOR
WXOR
Execution Pipeline
Multiply Pipeline
Memory Pipeline
Core Interface Pipeline
Delay (Clocks)
1
1
1
1
1
1
1
1
Intel® PXA27x Processor Family Optimization Guide