Intel PXA270 Optimization Manual page 84

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
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Issue Latency
The cycle distance from the first issue clock of the current instruction to the issue clock of the
next instruction. Cache-misses, resource-dependency stalls, and resource availability conflicts
can influence the actual number of cycles.
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Result Latency
The cycle distance from the first issue clock of the current instruction to the issue clock of the
first instruction using the result without incurring a resource dependency stall. Cache-misses,
resource-dependency stalls, and resource availability conflicts influence the actual number of
cycles.
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Minimum Issue Latency (without branch misprediction)
This represents the minimum cycle distance is the distance from the issue clock of the current
instruction to the first possible issue clock of the next instruction. For example, the issuing of
the next instruction is not stalled due to these situations:
— Resource dependency stalls
— The next instruction can be immediately fetched from the cache or memory interface
— The current instruction does not incur a resource dependency stall during execution that
can not be detected at its issue time
— The instruction uses dynamic branch prediction, correct prediction is assumed.
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Minimum Result Latency
This represents the required minimum cycle is the distance from the issue clock of the current
instruction to the issue clock of the first instruction that uses the result without incurring a
resource dependency stall. For example, the issuing of the next instruction is not stalled due to
these situations:
— Resource dependency stalls
— The next instruction can be immediately fetched from the cache or memory interface.
— The current instruction does not incur resource dependency stalls during executions that
cannot be detected at issue time.
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Minimum Issue Latency (with branch misprediction)
It represents the minimum cycle distance from the issue clock of the current branching
instruction to the first possible issue clock of the next instruction. The value of this is identical
to minimum issue latency except the branching instruction is mispredicted. It is calculated by
adding minimum issue latency (without branch misprediction) to the minimum branch latency
penalty cycles using
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Minimum Resource Latency
The minimum cycle distance from the issue clock of the current multiply instruction to the
issue clock of the next multiply instruction assuming the second multiply does not incur a data
dependency and is immediately available from the instruction cache or memory interface.
This code is an example of computing latencies:
UMLAL r6,r8,r0,r1
ADD r9,r10,r11
SUB r2,r8,r9
MOV r0,r1
4-36
Table 4-3 and Table 4-4.
Intel® PXA27x Processor Family Optimization Guide