Intel PXA270 Optimization Manual page 58

Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
In the following code sample, the ADD and LDR instructions can be moved before the MOV
instruction. This helps prevent pipeline stalls if the load hits the data cache. However, if the load is
likely to miss the data cache, move the LDR instruction so it executes as early as possible—before
the SUB instruction. Moving the LDR instruction before the SUB instruction changes the program
semantics.
; all other registers are in use
sub
mul
mov
orr
add
ldr
add
add
orr
; The value in register r6 is not used after this
It is possible to move the ADD and the LDR instructions before the SUB instruction so that the
contents of register R6 are allowed to spill and restore from the stack as shown in this example:
; all other registers are in use
str
add
ldr
mov
orr
add
ldr
add
orr
sub
mul
; The value in register R6 is not used after this
In the previous example, the contents of register R6 are spilled to the stack and subsequently
loaded back to register R6 to retain the program semantics. Using a preload instruction, such as the
one shown in the following example, is another way to optimize the code in the previous example.
; all other registers are in use
add
pld
sub
mul
mov
orr
ldr
add
4-10
r1, r6, r7
r3,r6, r2
r2, r2, LSL #2
r9, r9, #0xf
r0,r4, r5
r6, [r0]
r8, r6, r8
r8, r8, #4
r8,r8, #0xf
r6,[sp, #-4]!
r0,r4,r5
r6, [r0]
r2, r2, LSL #2
r9, r9, #0xf
r8, r6, r8
r6, [sp], #4
r8, r8, #4
r8,r8, #0xf
r1, r6, r7
r3,r6, r2
r0,r4, r5
[r0]
r1, r6, r7
r3,r6, r2
r2, r2, LSL #2
r9, r9, #0xf
r6, [r0]
r8, r6, r8
Intel® PXA27x Processor Family Optimization Guide