Intel Xscale® Microarchitecture And Intel Xscale® Core; Pxa27X Processor Block Diagram - Intel PXA270 Optimization Manual

Figure 1-1. PXA27x Processor Block Diagram
RTC
OS Timers
4 x PWM
Interrupt C
3 x SSP
USIM
2
I S
AC97
Full Function
Uart
Bluetooth
Uart
Fast IrDA
Slow IrDA
2
I C
USB
Client
Baseband
Interface
Keypad
Interface
SDcard/MMC
Interface
Mem Stick
Interface
Primary GPIO
1.2.1 Intel XScale® Microarchitecture and Intel XScale® core
The Intel XScale® Microarchitecture is based on a core that is ARM* version 5TE compliant. The
microarchitecture surrounds the core with instruction and data memory management units;
instruction, data, and mini-data caches; write, fill, pend, and branch-target buffers; power
management, performance monitoring, debug, and JTAG units; coprocessor interface; 32K caches;
MMUs; BTB; MAC coprocessor; and core memory bus.
The Intel XScale® Microarchitecture can be combined with peripherals to provide application-
specific standard products (ASSPs) targeted at selected market segments. For example, the RISC
core can be integrated with peripherals such as an LCD controller, multimedia controllers, and an
external memory interface to empower OEMs to develop smaller, more cost-effective handheld
devices with long battery life, with the performance to run rich multimedia applications. Or the
microarchitecture could be surrounded by high-bandwidth PCI interfaces, memory controllers, and
networking micro-engines to provide a highly integrated, low-power, I/O or network processor.
Intel® PXA27x Processor Family Optimization Guide
Internal
SRAM
DMA
Controller
System Bus
And
Bridge
Intel
XScale®
Core
13
Power Management
MHz
Clock Control
Osc
LCD
Memory
Controller
LCD
Address
Controller
and
Data
Variable
Latency I/O
Control
PCMCIA & CF
Control
Dynamic
USB
Memory
HOST
Control
Static
Memory
Control
32.768
KHz
Osc
Introduction
ASIC
Socket 0
XCVR
Socket 1
SDRAM/
SMROM
4 banks
ROM/
Flash/
SRAM
4 Banks
1-3