Memory Pipeline Thread; D1 Stage; D2 Stage; Dwb Stage - Intel PXA270 Optimization Manual

A forwarding path from the MWB stage to the RF stage serves as a non-critical bypass. Critical and
reasonable logic insertion are allowed.
2.3.3

Memory Pipeline Thread

2.3.3.1

D1 Stage

In the D1 pipe stage, the Intel XScale® Microarchitecture provides a virtual address that is used to
access the data cache. There is no logic inside the Intel® Wireless MMX™ Technology in the D1
pipe stage.
2.3.3.2

D2 Stage

The D2 stage is where load data is returned. Load data comes from either data cache or external
memory, with external memory having the highest priority. The Intel® Wireless MMX™
Technology needs to bridge incoming 32-bit data to internal 64-bit data.
2.3.3.3

DWB Stage

The DWB stage—the last stage of the D pipeline—is where load data is written back to the register
file.
Intel® PXA27x Processor Family Optimization Guide
Microarchitecture Overview
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