Frame Buffer Placement For Lcd Optimization - Intel PXA270 Optimization Manual

Table 3-6. Sample LCD Configurations with Latency and Peak Bandwidth Requirements
LCD (Base Plane Size, Refresh
Overlay 1, Overlay 2,
Cursor)
320x240+ No Overlay
640x480 + No Overlay
640x480 + No Overlay
800x600+ No Overlay
800x600 + 176x144
Overlay
3.5.1.2

Frame Buffer Placement for LCD Optimization

3.5.1.2.1 Internal Memory Usage
As the bandwidth and latency requirements increase with screen size, it may become necessary to
utilize internal memory in order to meet LCD requirements. Internal memory provides the lowest
latency and highest bandwidth of all memories in the system. In addition, having the frame buffer
located in internal SRAM dramatically reduces the external memory traffic in the system and the
internal bus-utilization.
3.5.1.2.2 Overlay Placement
Most systems that use overlays require more memory for the frame buffers (base plane and
overlays) than is available (or allocated for frame buffer usage) in the internal SRAM. Optimum
system performance is achieved by placing the most frequently accessed frame buffers in internal
SRAM and placing the remainder in external memory. Frame buffer accesses include not only the
OS and applications writing to the plane when updating the content displayed, but also the LCD
controller reading the data from the plane.
For the base plane the total accesses are simply the sum of the refresh rate plus the frequency of
content update of the base plane. For each overlay the total accesses are the same sum multiplied
by the percent of time the overlay is enabled. After estimating the total accesses for the base plane
and all overlays employed, place the frame buffers for the planes with the highest total accesses in
the internal SRAM.
Some systems might benefit from dynamically reconfiguring the location of the frame buffer
memory whenever the overlays are enabled. When overlays are disabled the frame buffer for the
base plane is placed in the internal SRAM. However, when the overlays are enabled, the base
plane's frame buffer is moved to external memory and the frame buffers of the overlays are placed
in the internal SRAM. This method requires close coordination with the LCD controller to ensure
that no artifacts are seen on the LCD. Refer to the LCD chapter in the Intel® PXA27x Processor
Family Developer's Manual for more information on reconfiguring the LCD.
Intel® PXA27x Processor Family Optimization Guide
Frame Buffer
Color Foot Print
Rate
Depth Requirement
(Hz)
(KBytes)
77 16 BPP 150
18 BPP
78 1200
unpacked
18 BPP
78 900
packed
73 16 BPP 937.5
937.5 base + 49.5
73 16 BPP
overlay
System Level Optimization
Average
Maximum
Bandwidth
Latency
Requirements
Tolerance (ns)
(MBytes/Sec)
2702.56 11.28
333.87 91.41
445.16 68.55
456.62 66.83
223.78 70.52
Peak Bandwidth
Requirements
(MBytes / sec)
11.28
91.41
68.55
66.83
133.67
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