Intel PXA270 Optimization Manual page 140

Index
G
General Optimization Techniques 1
General Pipeline Characteristics 1
General Remarks on Multi-Sample Technique 25
General Remarks on Software Pipelining 23
Global versus Local Variables 14
H
Half-Turbo Mode 4
High Level Language Optimization 1
2
High-Level Overview
High-Level Pipeline Organization
I
ID Stage 7
Idle Mode 2, 6
If-else versus Switch Statements 12
Implicit Accumulator Access Instruction Timings
Improved Caching and Internal Memory Usage 5
Increasing Data Cache Performance 5
Increasing Instruction Cache Performance 4
Increasing Load Throughput 11
Increasing Load Throughput on Intel® Wireless MMX™
Technology 18
Increasing Preloads for Memory Performance 10
Increasing Store Throughput 12
Instruction Decode (ID) Pipestage 4
Instruction Flow Through the Pipeline 2
Instruction Latencies for Intel XScale® Microarchitecture 35
Instruction Latencies for Intel® Wireless MMX™ Technolo-
gy 43
Instruction Scheduling for Intel XScale® Microarchitecture 8
Instruction Scheduling for Intel XScale® Microarchitecture
and Intel® Wireless MMX™ Technology 8
Instruction Scheduling for Intel® Wireless MMX™ Technol-
ogy 18
Intel XScale® Microarchitecture & Intel® Wireless MMX™
Technology Optimization 1
Intel XScale® Microarchitecture and Intel XScale® core
Intel XScale® Microarchitecture Compatibility
Intel XScale® Microarchitecture Features
Intel XScale® Microarchitecture Pipeline 1
Intel XScale® Microarchitecture RISC Superpipeline
Intel® Performance Primitives 34
Intel® Wireless MMX™ technology
Intel® Wireless MMX™ Technology Instruction Mapping 27
Intel® Wireless MMX™ Technology Pipeline 7
Intel® Wireless MMX™ Technology Pipeline Threads and
relation with Intel XScale® Microarchitecture Pipe-
7
line
Interleaved Pack with Saturation Example 29
5
Internal Memories
Internal Memory Usage 13
Internal SRAM Access Latency and Throughput for Different
Frequencies (Silicon Measurement Pending)
1
Introduction , 1
Issue Clock (cycle 0) 35
Index-2
46
40
3
8
4
1
4
2
Issue Cycle and Result Latency of the PXA27x processor In-
43
structions
Issue Latency 36
L
37
Latency Example
LCD Color Conversion HW 14
LCD Controller Optimization 11
6
LCD Display Controller
LCD Display Frame Buffer Setting 14
LCD Frame Buffer 9
LCD Subsystem 5
Load and Store Instruction Timings
Load and Store Multiple Instruction Timings
Load/Store Instructions 41
Locality in Source Code 12
Locking Code into the Instruction Cache 5
Loop Conditionals 11
Loop Fusion 9
Loop Interchange 8
Loop Unrolling 9
M
M1 Stage 8
M2 Stage 8
M3 Stage 8
Main Execution Pipeline 3
5
Memory Architecture
Memory Control Pipeline 48
Memory Pipeline 5
Memory Pipeline Thread 9
Memory System Optimization 1
Memory to Memory Performance Using DMA for Different
Memories and Frequencies
Microarchitecture Overview 1
Minimum Issue Latency (with branch misprediction) 36
Minimum Issue Latency (without branch misprediction) 36
Minimum Resource Latency 36
Minimum Result Latency 36
Miscellaneous Instruction Timing 42
Multiple Descriptor Technique 14
Multiple Pipelines 49
Multiply Implicit Accumulate Instruction Timings
Multiply Instruction Timings 39,
Multiply pipe instruction classes
Multiply Pipeline 47
Multiply Pipeline Thread 8
Multiply/Multiply Accumulate (MAC) Pipeline 5
Multi-Sample Technique 23
MWB Stage 8
N
Nested If-else and Switch Statements 12
Normal Mode 1, 6
Number of Parameters in Functions 14
Intel® PXA27x Processor Family Optimization Guide
41
41
17
40
39
48