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System Level Optimization
Maximum plane overlap is the maximum number of overlapping planes (base, overlay 1, overlay
2). The planes do not need to completely overlap each other, they simply need to occupy the same
pixel location. It is generally the number of planes used, unless the overlays are guaranteed never
to be positioned over one another. The peak bandwidth is required whenever the LCD controller is
displaying a portion of the screen where the planes overlap. While the peak bandwidth is higher
than the average bandwidth, it does not sustain for long. Sustained period of peak bandwidth
activity is dependent on the overlay sizes and color depth.
The system needs to guarantee the LCD has enough bandwidth available to meet peak bandwidth
requirements for the sustained peak-bandwidth period to avoid underruns during plane overlap
periods. Optimizing arbitration scheme and internal memory usage is encouraged to address this
problem. The LCD controller has an internal buffering mechanism to minimize the impact of
fluctuations in the bandwidths.
The maximum latency the LCD controller can tolerate for it's 32-byte burst data fetches can be
calculated with the equation below. Note that the latency requirements may vary for different
overlays (refer to
Requirements").
Peak bandwidth comes from the equation above and is in bytes per second.
•
So, for example, a 640x480x16 BPP screen with a 320x240x16BPP overlay and a 70 Hz
refresh rate, average bandwidth required is:
[(480 x 640 x 70 x 16) / 8] + [(240 x 320 x 70 x 16) / 8]
= 43008000 + 10752000
= 53,760,000 bytes per sec, or 52 MBytes/sec.
•
The Peak bandwidth required is:
2 x [(480 x 640 x 70 x 16) / 8] = 86,016,000 bytes per sec, or 82 Mbytes per sec.
•
The Maximum allowable average latency for LCD DMA burst data fetches is:
32 / 86,016,000 = 372 ns,
•
For a 195 MHz system bus, this is (372 x 10
Note that each LCD DMA channel has a 16-entry, 8-byte wide FIFO buffer to help deal with
fluctuations in available bandwidth due to spikes in system activity.
3-12
Table 3-6, "Sample LCD Configurations with Latency and Peak Bandwidth
Latency
=
- - - - - - - - - - - - - - - - - - - - - - - - - - -
Peak Bandwidth
Intel® PXA27x Processor Family Optimization Guide
seconds
32
-9
6
) x (195 x 10
) = 72 system bus cycles
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