Intel PXA270 Optimization Manual page 141

O
Operating Mode Recommendations for Power Savings 6
Optimal Setting for Memory Latency and Bandwidth 1
Optimization of System Components 10
Optimizations for Core Power 1
Optimizations for Memory and Peripheral Power 5
Optimizing Arbiter Settings 15
Optimizing Complex Expressions 5
Optimizing for Instruction and Data Caches 4
Optimizing for Internal Memory Usage 9
Optimizing Frequency Selection 1
Optimizing Integer Multiply and Divide 7
Optimizing Libraries for System Performance 29
Optimizing the Use of Immediate Values 6
Optimizing TLB (Translation Lookaside Buffer) Usage 8
OS Acceleration 10
Other General Optimizations 14
6
Other Peripherals
Out of Order Completion 2
Overlay Placement 13
P
Page Attributes For Data Access 3
Page Attributes For Instructions 3
Page Table Configuration 3
Performance Checklist 1
Performance Hazards 45
Performance Optimization Tips 1
Performance Terms 35
Perils of Superpipelining 6
6
Peripheral Bus
Peripheral Bus Split Transactions 17
Peripheral Clock Gating 5
Peripherals in the Processor
Pipeline Organization 1
Pipeline Stalls 3
2
Pipelines and Pipe Stages
Placing Literal Pools 14
Porting Existing MMX™ Technology Code to Intel® Wire-
less MMX™ Technology 26
3
Power
Power Modes and Typical Power Consumption Summary
Power Optimization 1
Power Optimization Guidelines 2
Preload Considerations 1
Preload Distances In the Intel XScale® Microarchitecture 1
Preload Limitations
Bandwidth Consumption 3
Low Number of Iterations 3
Throughput bound vs. Latency bound 3
Preload Loop Limitations 3
Preload Loop Scheduling 2
preload scheduling distance (PSD) 2
Processor Internal Communications
Program Flow and Branch Instructions 2
PXA27x Processor Block Diagram
PXA27x processor Mapping to Intel® Wireless MMX™
Intel® PXA27x Processor Family Optimization Guide
6
5
3
Technology and SSE
PXA27x Processor Performance Features
R
Read Buffer Behavior 5
Reducing Cache Conflicts, Pollution and Pressure 8
Reducing Memory Page Thrashing 7
Register File / Shifter (RF) Pipestage 4
Resource Availability Delay for the Coprocessor Interface
49
Pipeline
Resource Availability Delay for the Execution Pipeline
Resource Availability Delay for the Memory Pipeline
Resource Availability Delay for the Multiplier Pipeline
Resource Hazard 45
Result Latency 36
RF Stage 7
Round Robin Replacement Cache Policy 5
S
Sample LCD Configurations with Latency and Peak Band-
width Requirements
Saturated Arithmetic Instructions 40
Saturated Data Processing Instruction Timings
Scheduling Coprocessor 15 Instructions 18
Scheduling Data-Processing 15
Scheduling Load and Store Multiple (LDM/STM) 14
Scheduling Load Double and Store Double (LDRD/STRD) 13
Scheduling Loads 8
Scheduling MRS and MSR Instructions 17
Scheduling Multiply Instructions 15
Scheduling SWP and SWPB Instructions 16
Scheduling the MRA and MAR Instructions (MRRC/MCRR)
17
Scheduling the TMIA Instruction 20
Scheduling the WMAC Instructions 19
Scheduling the WMUL and WMADD Instructions 21
Scratch Ram 10
SDRAM Auto Power Down (APD) 5
Semaphore Instruction Timings
Semaphore Instructions 42
3 Signed Unpack Example 29
SIMD Optimization Techniques 21
Sleep Mode 2, 7
Software Pipelining 21
Standby Mode 2, 7
Status Register Access Instruction Timings
Status Register Access Instructions 41
Switching Modes for Saving Power 1
5
System Bus
System Bus Frequency Selection 3
System Level Optimization 1
T
Taking Advantage of Bus Parking 16
Thumb* Instructions 43
Index
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8
46
48
48
13
40
42
41
Index-3