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Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
Table 4-20. Multiply pipe instruction classes
WMAC, WMUL, WMADD
WSAD, TMIAph, TMIAxy
Table 4-21. Resource Availability Delay for the Multiplier Pipeline
Instruc-
tions
WSAD
WACC
WMUL
WMADD
WMAC
TMIA
TMIAPH
TMIAxy
WSAD, TMIA, TMIAxy, TMIAph execute in both the main execution pipeline and the multiplier
pipeline. See
4.10.2.3
Memory Control Pipeline
The memory control pipeline is responsible for coordinating the load/store activity with the main
core. The external interface to memory is 32-bits so the 64-bit load/store issued by the PXA27x
processor device are sequenced as two 32-bit load/stores to memory. This is transparent to end
users and is already factored into the result latencies show in
processor device issues the 64-bit memory transaction, it must buffer the data until the two 32-bit
half transactions are complete. Currently, there are two 64-bit buffer slots for load operations and
one 64-bit buffer slot available for store transactions. If the memory buffer is currently empty, the
Memory pipeline resource- availability delay is only one clock. However, if the buffer is currently
full due to a sequence of memory transactions, the following instruction must wait for space in the
buffer. The resource availability delay in this case is two cycles. This is summarized in
Table 4-22. Resource Availability Delay for the Memory Pipeline
4-48
Instructions
WACC
TMIA
Delay(Clocks) for a
Delay(Clocks) for a
subsequent class 1
subsequent class 2
multiply pipe
multiply pipe
instruction
instruction
2
1
2
2
2
3
2
2
Section 4.10.2.5
for more details
Instructions
WLDRD
WSTRD
WLDRD
Class
1
2
3
4
Delay(Clocks) for a
subsequent class 3
multiply pipe
instruction
2
1
1
1
2
1
2
1
2
1
3
2
2
1
2
1
Table
Delay(Clocks)
1
Two loads not already outstanding
2
Two loads already outstanding (M is
3+M
delay for main memory if cache miss)
Intel® PXA27x Processor Family Optimization Guide
Delay(Clocks) for a
subsequent class 4
multiply pipe
instruction
1
1
1
1
1
2
1
1
4-18. After the PXA27x
Table
Condition
4-22.
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