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Intel XScale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization
4.8.4
Multiply Instruction Timings
Table 4-6. Multiply Instruction Timings (Sheet 1 of 2)
Instruction
MLA
MUL
SMLAL
SMLALxy
SMLAWy
SMLAxy
SMULL
SMULWy
SMULxy
UMLAL
Intel® PXA27x Processor Family Optimization Guide
Rs Value
S-Bit
(Early Termination)
Value
Rs[31:15] = 0x00000
0
or
1
Rs[31:15] = 0x1FFFF
Rs[31:27] = 0x00
0
or
1
Rs[31:27] = 0x1F
0
all others
1
Rs[31:15] = 0x00000
0
or
1
Rs[31:15] = 0x1FFFF
Rs[31:27] = 0x00
0
or
1
Rs[31:27] = 0x1F
0
all others
1
Rs[31:15] = 0x00000
0
or
1
Rs[31:15] = 0x1FFFF
Rs[31:27] = 0x00
0
or
1
Rs[31:27] = 0x1F
0
all others
1
N/A
N/A
N/A
N/A
N/A
N/A
Rs[31:15] = 0x00000
0
or
1
Rs[31:15] = 0x1FFFF
Rs[31:27] = 0x00
0
or
1
Rs[31:27] = 0x1F
0
all others
1
N/A
N/A
N/A
N/A
0
Rs[31:15] = 0x00000
1
0
Rs[31:27] = 0x00
1
0
all others
1
Minimum
Minimum Result
Issue Latency
Latency
1
2
2
2
1
3
3
3
1
4
4
4
1
2
2
2
1
3
3
3
1
4
4
4
2
RdLo = 2; RdHi = 3
3
3
2
RdLo = 3; RdHi = 4
4
4
2
RdLo = 4; RdHi = 5
5
5
2
RdLo = 2; RdHi = 3
1
3
1
2
1
RdLo = 2; RdHi = 3
3
3
1
RdLo = 3; RdHi = 4
4
4
1
RdLo = 4; RdHi = 5
5
5
1
3
1
2
2
RdLo = 2; RdHi = 3
3
3
2
RdLo = 3; RdHi = 4
4
4
2
RdLo = 4; RdHi = 5
5
5
Minimum Resource
†
Latency (Throughput)
1
2
2
3
3
4
1
2
2
3
3
4
2
3
3
4
4
5
2
2
1
2
3
3
4
4
5
2
1
2
3
3
4
4
5
4-39
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