Intel PXA270 Optimization Manual page 6

Contents
4.8.3 Data Processing Instruction Timings ..................................................................4-38
4.8.4 Multiply Instruction Timings ................................................................................4-39
4.8.5 Saturated Arithmetic Instructions........................................................................4-40
4.8.6 Status Register Access Instructions ...................................................................4-41
4.8.7 Load/Store Instructions.......................................................................................4-41
4.8.8 Semaphore Instructions......................................................................................4-42
4.8.9 CP15 and CP14 Coprocessor Instructions .........................................................4-42
4.8.10 Miscellaneous Instruction Timing........................................................................4-42
4.8.11 Thumb* Instructions............................................................................................4-43
4.9 Instruction Latencies for Intel® Wireless MMX™ Technology.........................................4-43
4.10 Performance Hazards......................................................................................................4-45
4.10.1 Data Hazards......................................................................................................4-45
4.10.2 Resource Hazard................................................................................................4-45
4.10.2.1 Execution Pipeline ..............................................................................4-46
4.10.2.2 Multiply Pipeline ..................................................................................4-47
4.10.2.3 Memory Control Pipeline.....................................................................4-48
4.10.2.4 Coprocessor Interface Pipeline...........................................................4-49
4.10.2.5 Multiple Pipelines ................................................................................4-49
5 High Level Language Optimization...........................................................................................5-1
5.1 C and C++ Level Optimization...........................................................................................5-1
5.1.1 Efficient Usage of Preloading ...............................................................................5-1
5.1.1.1
5.1.1.2
5.1.1.3
5.1.2 Array Merging .......................................................................................................5-6
5.1.3 Cache Blocking.....................................................................................................5-8
5.1.4 Loop Interchange..................................................................................................5-8
5.1.5 Loop Fusion ..........................................................................................................5-9
5.1.6 Loop Unrolling.......................................................................................................5-9
5.1.7 Loop Conditionals ...............................................................................................5-11
5.1.8 If-else versus Switch Statements........................................................................5-12
5.1.9 Nested If-Else and Switch Statements ...............................................................5-12
5.1.10 Locality in Source Code......................................................................................5-12
5.1.11 Choosing Data Types .........................................................................................5-12
5.1.12 Data Alignment For Maximizing Cache Usage ...................................................5-12
5.1.13 Placing Literal Pools ...........................................................................................5-14
5.1.14 Global versus Local Variables ............................................................................5-14
5.1.15 Number of Parameters in Functions ...................................................................5-14
5.1.16 Other General Optimizations ..............................................................................5-14
6 Power Optimization ....................................................................................................................6-1
6.1 Introduction ........................................................................................................................6-1
6.2 Optimizations for Core Power............................................................................................6-1
6.2.1 Code Optimization for Power Consumption..........................................................6-1
6.2.2 Switching Modes for Saving Power ......................................................................6-1
6.2.2.1
6.2.2.2
6.2.2.3
6.2.2.4
6.2.2.5
vi
Preload Considerations.........................................................................5-1
Preload Loop Limitations ......................................................................5-3
Coding Technique with Preload............................................................5-4
Normal Mode ........................................................................................6-1
Idle Mode ..............................................................................................6-2
Deep Idle Mode.....................................................................................6-2
Standby Mode.......................................................................................6-2
Sleep Mode...........................................................................................6-2
Intel® PXA27x Processor Family Optimization Guide