Intel PXA270 Optimization Manual page 8

Contents
4-2 Latency Example .....................................................................................................................4-37
4-3 Branch Instruction Timings (Those Predicted By the BTB (Branch Target Buffer)) ................4-37
4-4 Branch Instruction Timings (Those Not Predicted By the BTB)...............................................4-37
4-5 Data Processing Instruction Timings .......................................................................................4-38
4-6 Multiply Instruction Timings .....................................................................................................4-39
4-7 Multiply Implicit Accumulate Instruction Timings .....................................................................4-40
4-8 Implicit Accumulator Access Instruction Timings.....................................................................4-40
4-9 Saturated Data Processing Instruction Timings ......................................................................4-40
4-10 Status Register Access Instruction Timings ............................................................................4-41
4-11 Load and Store Instruction Timings.........................................................................................4-41
4-12 Load and Store Multiple Instruction Timings ...........................................................................4-41
4-13 Semaphore Instruction Timings...............................................................................................4-42
4-14 CP15 Register Access Instruction Timings .............................................................................4-42
4-15 CP14 Register Access Instruction Timings .............................................................................4-42
4-16 Exception-Generating Instruction Timings...............................................................................4-42
4-17 Count Leading Zeros Instruction Timings................................................................................4-42
4-18 Issue Cycle and Result Latency of the PXA27x processor Instructions ..................................4-43
4-19 Resource Availability Delay for the Execution Pipeline ...........................................................4-46
4-20 Multiply pipe instruction classes ..............................................................................................4-48
4-21 Resource Availability Delay for the Multiplier Pipeline.............................................................4-48
4-22 Resource Availability Delay for the Memory Pipeline ..............................................................4-48
4-23 Resource Availability Delay for the Coprocessor Interface Pipeline........................................4-49
6-1 Power Modes and Typical Power Consumption Summary .......................................................6-3
viii Intel® PXA27x Processor Family Optimization Guide