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System Level Optimization
3.5.1.2.3
Multiple Descriptor Technique
Another technique for utilizing internal SRAM is the use of multiple-descriptor frames. This
technique can be used if the LCD controller underruns due to occasional slow memory accesses.
The frame buffer is split across two different chained descriptors for a particular LCD DMA
channel. Both descriptors can be stored in internal SRAM for speedy descriptor reloading. One
descriptor points to frame buffer source data in external memory, while the second descriptor
points to the remainder of the frame buffer in internal SRAM. The descriptor that points to frame
data in external memory should have the end of frame (EOF) interrupt bit set. The idea is to queue
slower memory transfers and push them out when the EOF interrupt occurs, indicating that the
LCD is switching to internal SRAM. This allows a ping-pong between slow memory traffic (that
would cause LCD output FIFO underruns) and LCD traffic. This technique is only necessary with
very large screens, and will not work if the offending slow memory accesses also occur when the
LCD is fetching from external memory.
3.5.1.3
LCD Display Frame Buffer Setting
For most products the LCD frame buffer is allocated in a noncacheable region. If this region is set
to noncached but bufferable graphics performance improvements can be achieved.
The noncached but bufferable mode (X=0, C=0, B=1) improves write performance by allowing the
consecutive writes to coalesce in the write buffer and result in more efficient bus transactions.
System developers should set their LCD frame buffer as noncached but bufferable.
3.5.1.4
LCD Color Conversion HW
The LCD controller is equipped with hardware color management capabilities such as:
•
Up-scaling from YCbCr 4:2:0 & 4:2:2 to YCbCr 4:4:4
•
Color Space Conversion from YCbCr 4:4:4 to RGB 8:8:8 (CCIR 601)
•
Conversion from RGB 8:8:8, to RGB 5:5:5 and the supported formats of RGBT
For many video and image applications, the color-conversion routines require a significant amount
of processing power. This work can be off-loaded to the LCD controller by properly configuring
the LCD controller. This has two advantages; first, the Intel XScale® core is not burdened with the
processing, and second, the LCD bandwidth consumption is lowered by using the lower bit
precision format.
3.5.1.5
Arbitration Scheme Tuning for LCD
The most important thing to do in order to enable larger screens is to reprogram the arbiter
ARBCTRL register. The default arbiter weight for the programmable clients is LCD=2, DMA=3
and XScale=4; this is only sufficient for very small screens. Typically the LCD needs to be the
highest weight of the programmable clients - this is discussed further in
Arbiter
Settings".
3-14
Intel® PXA27x Processor Family Optimization Guide
Section 3.5.2, "Optimizing
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