Details Of Output Signals - Mitsubishi Electric MELSEC iQ-R User Manual

Details of output signals

The following describes the details of the output signals for the A/D converter module which are assigned to the CPU module.
The I/O numbers (X/Y) described in this section are for the case when the start I/O number of the A/D converter module is set
to 0.
This section describes buffer memory addresses for CH1. For details on the buffer memory addresses for
CH2 and later, refer to the following.
Page 179 List of buffer memory addresses
CH1 Logging hold request
Low speed
Use this signal as a trigger to hold (stop) logging at any timing during the logging.
When 'CH1 Logging enable/disable setting' (Un\G535) is set to Disable (1), the on or off of 'CH1 Logging hold request' (Y1) is
ignored.
For details on the normal logging function, refer to the following.
Page 71 Normal Logging Function
■Device number
The following shows the device number of this output signal.
Signal name
Logging hold request
■Operation of the logging hold processing
• When 'CH1 Level trigger condition setting' (Un\G542) is set to Disable (0), the logging hold processing starts by turning on
'CH1 Logging hold request' (Y1).
• When 'CH1 Level trigger condition setting' (Un\G542) is not set to Disable (0), the logging hold processing starts when the
set trigger condition is satisfied after turning on 'CH1 Logging hold request' (Y1). When the level trigger is enabled, use this
signal as an interlock condition to operate the level trigger.
• If 'CH1 Logging hold request' (Y1) is turned off during the logging hold processing, the hold (stop) state is cleared and the
logging restarts.
The stop state of the logging can be checked with 'CH1 Logging hold flag' (Un\G409).
Operating condition setting request
Common
Turn on and off 'Operating condition setting request' (Y9) to enable the setting of the A/D converter module.
For the timing of turning on and off the signal, refer to the following.
Page 170 Operating condition setting completed flag
For details on the buffer memory areas to be enabled, refer to the following.
Page 179 List of buffer memory addresses
■Device number
The following shows the device number of this output signal.
Signal name
Operating condition setting request
APPX
176
Appendix 2 I/O Signals
CH1 CH2
Y1 Y2
CH1 CH2
Y9
CH3 CH4
Y3 Y4
CH3 CH4