Details Of Output Signals - Mitsubishi Electric MELSEC iQ-R Series User Manual

Details of output signals

The following describes the details of the output signals for the D/A converter module which are assigned to the CPU module.
The I/O numbers (X/Y) described in Appendix 2 are for the case when the start I/O number of the D/A converter module is set
to 0.
This section describes I/O signals and buffer memory addresses for CH1.
For details on the buffer memory addresses after CH2, refer to the following.
Page 124 List of buffer memory addresses
CH1 Output enable/disable flag
Set whether to output the D/A conversion value or offset value.
On: D/A conversion value
Off: Offset value
■Device number
The following shows the device number of this input signal.
Signal name
CH Output enable/disable flag
*1 For the R60DA4, using Y5 to Y8 is prohibited.
Operating condition setting request
Turn on and off Operating condition setting request (Y9) to enable the setting of the buffer memory address.
For the buffer memory addresses which require turning on and off of 'Operating condition setting request' (Y9) to enable the
changed values, refer to the following.
Page 124 List of buffer memory addresses
For the timing of turning the signal on and off, refer to the following.
Page 116 Operating condition setting completed flag
■Device number
The following shows the device number of this input signal.
Signal name
Operating condition setting request
CH1 CH2 CH3
Y1 Y2 Y3
CH1 CH2 CH3
Y9
CH4 CH5 CH6
*1 *1
Y4 Y5 Y6
CH4 CH5 CH6
Appendix 2 I/O Signals
CH7 CH8
*1 *1
Y7 Y8
A
CH7 CH8
APPENDICES
121