Details Of Input Signals - Mitsubishi Electric MELSEC iQ-R User Manual

Details of input signals

The following describes the details of the input signals for the A/D converter module which are assigned to the CPU module.
The I/O numbers (X/Y) described in this section are for the case when the start I/O number of the A/D converter module is set
to 0.
This section describes buffer memory addresses for CH1. For details on the buffer memory addresses for
CH2 and later, refer to the following.
Page 179 List of buffer memory addresses
Module READY
Common
Module READY (X0) turns on to indicate the preparation for the A/D conversion is completed after the power-on or after the
reset operation of the CPU module.
In the following cases, 'Module READY' (X0) turns off.
• In the offset/gain setting mode (In this case, the A/D conversion is performed.)
• When a watchdog timer error occurs in the A/D converter module (In this case, the A/D conversion is not performed.)
■Device number
The following shows the device number of this input signal.
Signal name
Module READY
Warning output signal
Medium speed Low speed
'Warning output signal' (X8) turns on when the process alarm or rate alarm has been detected. When the warning output
function is disabled for all channels, 'Warning output signal' (X8) is always off.
■Device number
The following shows the device number of this input signal.
Signal name
Warning output signal
■Process alarm
• 'Warning output signal' (X8) turns on when digital output values or digital operation values of the A/D conversion enabled
channels exceed the ranges of the process alarm lower lower limit value to the process alarm upper upper limit value after
'CH1 Warning output setting (Process alarm)' (Un\G512) is set to Enable (0). The ALM LED also turns on.
• 'Warning output signal' (X8) turns off when the digital output values or digital operation values fall within the setting range in
all the A/D conversion enabled channels. The ALM LED also turns off.
CH1
X0
Simultaneous
Synchronization
conversion
CH1
X8
CH2 CH3
CH2 CH3
Appendix 2 I/O Signals
CH4
A
CH4
APPX
169