Mitsubishi Electric MELSEC iQ-R User Manual page 193

Warning output flag (Rate alarm lower limit)
Medium speed Low speed
The lower limit warning of the rate alarm can be checked for each channel.
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0 0 0
(2)
(1) 0: Normal, 1: Alarm ON
(2) b4 to b15 are fixed to 0.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Warning output flag (Rate alarm lower limit)
■Warning output flag status
• When a value is out of the range specified in 'CH1 Rate alarm lower limit value' (Un\G526), Alarm ON (1) is stored in the
corresponding bit of 'Warning output flag (Rate alarm lower limit)' (Un\G39).
• When a warning is detected in any channel where the A/D conversion and the warning output setting (rate alarm) are
enabled, 'Warning output signal' (X8) also turns on.
■Clearing Warning output flag
• When the change rate of the digital output value falls within the set range, the flag is automatically cleared.
• When 'Operating condition setting request' (Y9) is turned on and off, the flag is cleared.
Input signal error detection flag
Medium speed Low speed
The status of an input signal can be checked for each channel.
b15 b14 b13 b12 b11 b10 b9
0 0 0 0 0 0 0
(2)
(1) 0: Normal, 1: Input signal error
(2) b4 to b15 are fixed to 0.
■Buffer memory address
The following shows the buffer memory address of this area.
Buffer memory name
Input signal error detection flag
■Input signal error detection flag status
• When an analog input value out of the range set with 'CH1 Input signal error detection lower limit setting value' (Un\G529)
and 'CH1 Input signal error detection upper limit setting value' (Un\G530) is detected, Input signal error (1) is stored in the
corresponding bit of 'Input signal error detection flag' (Un\G40).
• When an error is detected in any channel where the A/D conversion and the input signal error detection are enabled, 'Input
signal error detection signal' (XC) turns on.
b8 b7 b6 b5 b4 b3 b2
0 0 0 0 0 CH4 CH3 CH2
(1)
CH1
39
Simultaneous
Synchronization
conversion
b8 b7 b6 b5 b4 b3 b2
0 0 0 0 0 CH4 CH3 CH2
(1)
CH1
40
b1 b0
CH1
CH2
b1 b0
CH1
CH2
CH3 CH4
CH3 CH4
APPX
Appendix 3 Buffer Memory Areas
A
191