Common Registers Between Port Groups - Epson S1C17M20 Technical Manual

6 I/O PORTS (PPORT)
Register name Bit
PDFNCSEL 15–10 –
(Pd Port Function
9–8 PD4MUX[1:0]
Select Register)
7–6 PD3MUX[1:0]
5–4 PD2MUX[1:0]
3–2 PD1MUX[1:0]
1–0 PD0MUX[1:0]
PDSELy = 0
Port PDyMUX = 0x0
name (Function 0)
GPIO
Peripheral
Pd0 PD0 DBG
Pd1 PD1 DBG
Pd2 PD2 DBG
Pd3 PD3 –
Pd4 PD4 –

6.7.7 Common Registers between Port Groups

Table 6.7.7.1 Control Registers for Common Use with Port Groups
Register name Bit
PCLK 15–9 –
(P Port Clock Control
8
Register)
7–4 CLKDIV[3:0]
3–2 KRSTCFG[1:0]
1–0 CLKSRC[1:0]
PINTFGRP 15–8 –
(P Port Interrupt Flag
7–5 –
Group Register)
4
3
2
1
0
6-24
Bit name Initial
0x00
0x0
0x0
0x0
0x0
0x0
Table 6.7.6.2 Pd Port Group Function Assignment
PDyMUX = 0x1
(Function 1)
Pin Peripheral Pin
DST2 –
DSIO –
DCLK –
– –
– –
Bit name Initial
0x00
DBRUN 0
0x0
0x0
0x0
0x00
0x0
P4INT 0
P3INT 0
P2INT 0
P1INT 0
P0INT 0
Seiko Epson Corporation
Reset R/W
– R –
H0 R/W –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
PDSELy = 1
PDyMUX = 0x2
(Function 2)
Peripheral Pin Peripheral
– – –
– – –
– – –
– CLG OSC3
– CLG OSC4
Reset R/W
– R –
H0 R/WP –
H0 R/WP
H0 R/WP
H0 R/WP
– R –
– R
H0 R –
H0 R
H0 R
H0 R
H0 R
M20/M23 M21/
Remarks
24pin 32pin
– –
–
✓
–
✓
✓ ✓
✓ ✓
✓ ✓
PDyMUX = 0x3
M20/M23 M21/
(Function 3)
Pin
24pin 32pin
– –
✓ ✓
– –
✓ ✓
– –
✓ ✓
– – –
✓
–
– –
✓
M20/M23 M21/
Remarks
24pin 32pin
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
– –
– –
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
M22/
M24 M25
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
✓ ✓
M22/
M24 M25
✓ ✓
✓ ✓
✓ ✓
✓ ✓
✓ ✓
M22/
M24 M25
– –
✓ ✓
✓ ✓
✓ ✓
✓ ✓
– –
– –
–
✓
✓ ✓
✓ ✓
✓ ✓
✓ ✓