Slave Operations In 10-Bit Address Mode; Automatic Bus Clearing Operation - Epson S1C17M20 Technical Manual

14 I 2 C (I2C)

14.4.7 Slave Operations in 10-bit Address Mode

The I2C Ch.n functions as a slave device in 10-bit address mode when the I2CnCTL.MST bit = 0 and the I2CnMOD.
OADR10 bit = 1.
The following shows the address receiving operations in 10-bit address mode. Figure 14.4.7.1 shows an operation
example. See Figure 14.4.4.1 for the 10-bit address configuration.
10-bit address receiving operations
After a START condition is issued, the master sends the first address that includes the two high-order slave ad-
dress bits and the R/W bit (= 0). If the received two high-order slave address bits are matched with the I2CnO-
ADR.OADR[9:8] bits, the I2C Ch.n returns an ACK. At this time, other slaves may returns an ACK as the two
high-order bits may be matched.
Then the master sends the eight low-order slave address bits as the second address. If this address is matched
with the I2CnOADR.OADR[7:0] bits, the I2C Ch.n returns an ACK and starts data receiving operations.
If the master issues a request to the slave to send data (data reception in the master), the master generates a re-
peated START condition and sends the first address with the R/W bit set to 1. This reception switches the I2C
Ch.n to data sending mode.
At start of data reception
I 2 C bus S 1stAddr/W
BSY = 1
At start of data transmission
I 2 C bus S 1stAddr/W
BSY = 1
Figure 14.4.7.1 Example of Data Transfer Starting Operations in 10-bit Address Mode (Slave Mode)

14.4.8 Automatic Bus Clearing Operation

The I2C Ch.n set into master mode checks the SDA state immediately before generating a START condition. If SDA is
set to a low level at this time, the I2C Ch.n automatically executes bus clearing operations that output up to ten clocks
from the SCLn pin with SDA left free state.
When SDA goes high from low within nine clocks, the I2C Ch.n issues a START condition and starts normal opera-
tions. If SDA does not change from low when the I2C Ch.n outputs the ninth clock, it is regarded as an automatic bus
clearing failure. In this case, the I2C Ch.n clears the I2CnCTL.TXSTART bit to 0 and sets both the I2CnINTF.ERRIF
and I2CnINTF.STARTIF bits to 1.
14-14
Clock stretching by I2C
STARTIF = 1
A 2ndAddr A
TR = 0
STARTIF = 1
Clock stretching by I2C
STARTIF = 1
A 2ndAddr A Sr
TR = 0
STARTIF = 1
Software bit operations
Operations by the external master
S: START condition, Sr: Repeated START condition, P: STOP condition,
A: ACK, A: NACK, 1stAddr/W: 1st address + W(0), 1stAddr/R: 1st address + R(1),
2ndAddr: 2nd address, Data n: 8-bit data
Seiko Epson Corporation
→
RXD[7:0] Data 1
Data 1 A Data 2
RBFIF = 1
BYTEENDIF = 1
Data 1 → TXD[7:0]
1stAddr/R A Data 1
TR = 1 TBEIF = 1
STARTIF = 1
TBEIF = 1
Hardware bit operations
Operations by I2C (slave mode)
A
Data 2 → TXD[7:0]
A Data 2
TBEIF = 1
BYTEENDIF = 1
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)