Interrupts - Epson S1C17M20 Technical Manual

Cmos 16-bit single chip microcontroller
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17 IR REMOTE CONTROLLER (REMC3)
Example) REMDBCTL.TRMD bit = 0 (repeat mode), REMDBCTL.BUFEN bit = 1 (compare buffer enabled), REM-
DBCTL.REMOINV bit = 0 (signal logic non-inverted)
REMDBCTL.PRUN
16-bit counter for
data signal generation
0
(DBCNT[15:0])
REMAPLEN.APLEN[15:0]
REMDBLEN.DBLEN[15:0]
REMAPLEN buffer
REMDBLEN buffer
REMINTF.APIF
Compare AP interrupt
REMINTF.DBIF
Compare DB interrupt
REMINTF.DBCNTRUN
REMINTF.APLENBSY
REMINTF.DBLENBSY
Data signal
(Modulated data)
When the compare buffer is disabled (REMDBCTL.BUFEN bit = 0), the 16-bit counter value is directly compared
with the REMAPLEN.APLEN[15:0] and REMDBLEN.DBLEN[15:0] bit values. The comparison value is altered
immediately after the REMAPLEN.APLEN[15:0] or REMDBLEN.DBLEN[15:0] bits are rewritten.
When the compare buffer is enabled (REMDBCTL.BUFEN bit = 1), the REMAPLEN.APLEN[15:0] and REMD-
BLEN.DBLEN[15:0] bit values are loaded into the compare buffers provided respectively (REMAPLEN buffer and
REMDBLEN buffer) and the 16-bit counter value is compared with the compare buffers.
The comparison values are loaded into the compare buffers when the 16-bit counter is matched with the REM-
DBLEN buffer (when the count for the data length has completed). Therefore, the next transmit data can be set
during the current data transmission. When the compare buffers are enabled, the buffer status flags (REMINTF.
APLENBSY bit and REMINTF.DBLENBSY bit) become effective. The flag is set to 1 when the setting value is
written to the register and cleared to 0 when the written value is transferred to the buffer.

17.5 Interrupts

The REMC3 has a function to generate the interrupts shown in Table 17.5.1.
Interrupt
Interrupt flag
Compare AP REMINTF.APIF When the REMAPLEN register (or REMAPLEN
Compare DB REMINTF.DBIF When the REMDBLEN register (or REMDBLEN
The REMC3 provides interrupt enable bits corresponding to each interrupt flag. An interrupt request is sent to the in-
terrupt controller only when the interrupt flag, of which interrupt has been enabled by the interrupt enable bit, is set.
For more information on interrupt control, refer to the "Interrupt Controller" chapter.
17-6
0x0bd0
0x0bd1
1 2 3
0x0bd0
0x11b8
0x017a
0x0bd0
0x11b8
16T
Figure 17.4.4.1 Continuous Data Transmission Example
Table 17.5.1 REMC3 Interrupt Function
Set condition
buffer) value and the 16-bit counter for data signal
generation are matched
buffer) value and the 16-bit counter for data signal
generation are matched
Seiko Epson Corporation
0x11b8
0x00bd
0x00be
0
1
0x00bd
0x00bd
0x017a
Cleared
Cleared
8T
T
T
"0"
0x017a
0x00bd 0x00be
0x02f4
0
1
0x02f4
0x017a
0x00bd
0x02f4
Cleared
Cleared
Cleared
T
3T
"1"
Clear condition
Writing 1 to the interrupt flag or
the REMDBCTL.REMCRST bit
Writing 1 to the interrupt flag or
the REMDBCTL.REMCRST bit
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
0
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