Epson S1C17M20 Technical Manual page 95

Bits 9–0 CMP[9:0]
These bits set the NMI/reset generation cycle.
The value set in this register is compared with the 10-bit counter value while WDT2 is running, and
an NMI or reset is generated when they are matched.
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Seiko Epson Corporation
8 WATCHDOG TIMER (WDT2)
8-5