Epson S1C17M20 Technical Manual page 254

20 Multiplier/Divider (COPRO2)
Mode set-
Instruction
ting value
0x02
ld.cf %rd,%rs
(ext
imm9)
ld.cf %rd,imm7
S1C17 Core
Mode set-
Instruction
ting value
0x08
ld.ca %rd,%rs
or 0x09
(ext
imm9)
ld.ca %rd,imm7
0x18
ld.ca %rd,%rs
or 0x19
(ext
imm9)
ld.ca %rd,imm7
0x28
ld.ca %rd,%rs
or 0x29
(ext
imm9)
ld.ca %rd,imm7
0x38
ld.ca %rd,%rs
or 0x39
(ext
imm9)
ld.ca %rd,imm7
20-4
Table 20.4.1 Initializing the Operation Result Register 0 (32 bits)
Operations
res0[31:16] ← %rd
res0[15:0] ← %rs
res0[31:16] ← %rd
res0[15:0] ← imm7/16
COPRO2
Argument 2
Argument 1
Remainder
Coprocessor
output (16 bits)
Flag output
Figure 20.4.2 Data Path in Division Mode
Table 20.4.2 Operation in Division Mode
Operations
res0[31:0] ÷ {%rd, %rs}
res0[31:0] ← Quotient
res1[31:0] ← Remainder
%rd ← res0[15:0] (Quotient)
res0[31:0] ÷ {%rd, imm7/16}
res0[31:0] ← Quotient
res1[31:0] ← Remainder
%rd ← res0[15:0] (Quotient)
res0[31:0] ÷ {%rd, %rs}
res0[31:0] ← Quotient
res1[31:0] ← Remainder
%rd ← res0[31:16] (Quotient)
res0[31:0] ÷ {%rd, imm7/16}
res0[31:0] ← Quotient
res1[31:0] ← Remainder
%rd ← res0[31:16] (Quotient)
res0[31:0] ÷ {%rd, %rs}
res0[31:0] ← Quotient
res1[31:0] ← Remainder
%rd ← res1[15:0] (Remainder)
res0[31:0] ÷ {%rd, imm7/16}
res0[31:0] ← Quotient
res1[31:0] ← Remainder
%rd ← res1[15:0] (Remainder)
res0[31:0] ÷ {%rd, %rs}
res0[31:0] ← Quotient
res1[31:0] ← Remainder
%rd ← res1[31:16] (Remainder)
res0[31:0] ÷ {%rd, imm7/16}
res0[31:0] ← Quotient
res1[31:0] ← Remainder
%rd ← res1[31:16] (Remainder)
Seiko Epson Corporation
16 bits
÷
32 bits
Operation result Operation result
register 1 register 0
Selector
Flags
psr (CVZN) ← 0b0000 The operation result regis-
res0: operation result register 0, res1: operation result register 1
Remarks
res0: operation result register 0
32 bits
Quotient
Remarks
ters 0 and 1 keep the op-
eration results until they are
rewritten by other opera-
tion.
COPRO2 does not support
0 ÷ 0 division.
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)