Epson S1C17M20 Technical Manual page 8

CONTENTS
12 UART (UART3) ............................................................................................................12-1
12.1 Overview ...................................................................................................................... 12-1
12.2 Input/Output Pins and External Connections .............................................................. 12-2
12.2.1 List of Input/Output Pins ................................................................................ 12-2
12.2.2 External Connections .................................................................................... 12-2
12.2.3 Input Pin Pull-Up Function............................................................................. 12-2
12.2.4 Output Pin Open-Drain Output Function ...................................................... 12-2
12.2.5 Input/Output Signal Inverting Function .......................................................... 12-2
12.3 Clock Settings .............................................................................................................. 12-2
12.3.1 UART3 Operating Clock ................................................................................ 12-2
12.3.2 Clock Supply in SLEEP Mode ....................................................................... 12-3
12.3.3 Clock Supply in DEBUG Mode ...................................................................... 12-3
12.3.4 Baud Rate Generator ..................................................................................... 12-3
12.4 Data Format ................................................................................................................. 12-3
12.5 Operations ................................................................................................................... 12-4
12.5.1 Initialization .................................................................................................... 12-4
12.5.2 Data Transmission ......................................................................................... 12-5
12.5.3 Data Reception .............................................................................................. 12-6
12.5.4 IrDA Interface ................................................................................................. 12-7
12.5.5 Carrier Modulation ......................................................................................... 12-7
12.6 Receive Errors .............................................................................................................. 12-8
12.6.1 Framing Error ................................................................................................. 12-8
12.6.2 Parity Error ..................................................................................................... 12-8
12.6.3 Overrun Error ................................................................................................. 12-9
12.7 Interrupts ...................................................................................................................... 12-9
12.8 Control Registers ......................................................................................................... 12-9
UART3 Ch.n Clock Control Register ........................................................................................ 12-9
UART3 Ch.n Mode Register .................................................................................................... 12-10
UART3 Ch.n Baud-Rate Register ........................................................................................... 12-11
UART3 Ch.n Control Register ................................................................................................. 12-12
UART3 Ch.n Transmit Data Register ....................................................................................... 12-12
UART3 Ch.n Receive Data Register ........................................................................................ 12-12
UART3 Ch.n Status and Interrupt Flag Register ..................................................................... 12-13
UART3 Ch.n Interrupt Enable Register.................................................................................... 12-14
UART3 Ch.n Carrier Waveform Register ................................................................................. 12-14
13 Synchronous Serial Interface (SPIA) ........................................................................13-1
13.1 Overview ...................................................................................................................... 13-1
13.2 Input/Output Pins and External Connections .............................................................. 13-2
13.2.1 List of Input/Output Pins ................................................................................ 13-2
13.2.2 External Connections .................................................................................... 13-2
13.2.3 Pin Functions in Master Mode and Slave Mode ............................................ 13-3
13.2.4 Input Pin Pull-Up/Pull-Down Function .......................................................... 13-3
13.3 Clock Settings .............................................................................................................. 13-3
13.3.1 SPIA Operating Clock .................................................................................... 13-3
13.3.2 Clock Supply in DEBUG Mode ...................................................................... 13-4
13.3.3 SPI Clock (SPICLKn) Phase and Polarity ...................................................... 13-4
13.4 Data Format ................................................................................................................. 13-5
13.5 Operations ................................................................................................................... 13-5
13.5.1 Initialization .................................................................................................... 13-5
13.5.2 Data Transmission in Master Mode ............................................................... 13-5
13.5.3 Data Reception in Master Mode .................................................................... 13-7
13.5.4 Terminating Data Transfer in Master Mode .................................................... 13-8
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Seiko Epson Corporation
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)