Itc Interrupt Request Processing; Conditions To Accept Interrupt Requests By The Cpu; Nmi; Software Interrupts - Epson S1C17M20 Technical Manual

5 INTERRUPT CONTROLLER (ITC)

5.4.2 ITC Interrupt Request Processing

On receiving an interrupt signal from a peripheral circuit, the ITC sends an interrupt request, the interrupt level,
and the vector number to the CPU. Vector numbers are determined by the ITC internal hardware for each interrupt
cause, as shown in Table 5.2.1. The interrupt level is a value to configure the priority, and it can be set to between 0
(low) and 7 (high) using the ITCLVx.ILVx[2:0] bits provided for each interrupt source. The default ITC settings are
level 0 for all maskable interrupts. Interrupt requests are not accepted by the CPU if the level is 0.
The ITC outputs the interrupt request with the highest priority to the CPU in accordance with the following condi-
tions if interrupt requests are input to the ITC simultaneously from two or more peripheral circuits.
• The interrupt with the highest interrupt level takes precedence.
• If multiple interrupt requests are input with the same interrupt level, the interrupt with the lowest vector number
takes precedence.
The other interrupts occurring at the same time are held until all interrupts with higher priority levels have been ac-
cepted by the CPU.
If an interrupt cause with higher priority occurs while the ITC is outputting an interrupt request signal to the CPU
(before being accepted by the CPU), the ITC alters the vector number and interrupt level signals to the setting in-
formation on the more recent interrupt. The previously occurring interrupt is held. The held interrupt is canceled
and no interrupt is generated if the interrupt flag in the peripheral circuit is cleared via software.
Note: Before changing the interrupt level, make sure that no interrupt of which the level is changed can
be generated (the interrupt enable bit of the peripheral circuit is set to 0 or the peripheral circuit
is deactivated).

5.4.3 Conditions to Accept Interrupt Requests by the CPU

The CPU accepts an interrupt request sent from the ITC when all of the following conditions are met:
• The IE (Interrupt Enable) bit of the PSR has been set to 1.
• The interrupt request that has occurred has a higher interrupt level than the value set in the IL[2:0] (Interrupt
Level) bits of the PSR.
• No other interrupt request having higher priority, such as NMI, has occurred.

5.5 NMI

The watchdog timer embedded in this IC can generate a non-maskable interrupt (NMI). This interrupt takes prece-
dence over other interrupts and is unconditionally accepted by the CPU.
For detailed information on generating NMI, refer to the "Watchdog Timer" chapter.

5.6 Software Interrupts

The CPU provides the "int imm5" and "intl imm5, imm3" instructions allowing the software to generate any inter-
rupts. The operand imm5 specifies a vector number (0–31) in the vector table. In addition to this, the intl instruction
has the operand imm3 to specify the interrupt level (0–7) to be set to the IL[2:0] bits in the PSR. The software inter-
rupt cannot be disabled (non-maskable interrupt). The processor performs the same interrupt processing operation
as that of the hardware interrupt.
5-4
Seiko Epson Corporation
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)