Cpu And Debugger; Overview - Epson S1C17M20 Technical Manual

3 CPU and Debugger

3.1 Overview

This IC incorporates the Seiko Epson original 16-bit CPU core (S1C17) with a debugger. The main features of the
CPU core are listed below.
• Seiko Epson original 16-bit RISC processor
- 24-bit general-purpose registers: 8
- 24-bit special registers:
- 8-bit special register:
- Up to 16M bytes of memory space (24-bit address)
- Harvard architecture using separated instruction bus and data bus
• Compact and fast instruction set optimized for development in C language
- Code length:
- Number of instructions:
- Execution cycle:
- Extended immediate instructions: Immediate data can be extended up to 24 bits.
• Supports reset, NMI, address misaligned, debug, and external interrupts.
- Reads a vector from the vector table and branches to the interrupt handler routine directly.
- Can generate software interrupts with a vector number specified (all vector numbers specifiable).
• HALT mode (halt instruction) and SLEEP mode (slp instruction) are provided as the standby function.
• Incorporates a debugger with three-wire communication interface to assist in software development.
SYSCLK
NMI
Interrupt request
Interrupt
Interrupt level
controller
Vector number
Flash
Instruction bus
memory
RAM bus
RAM
Internal bus
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
2
1
16-bit fixed length
111 basic instructions (184 including variations)
Main instructions are executed in one cycle.
CPU core (S1C17)
General-purpose registers
Bit 23
R7
R6
R5
R4
R3
R2
R1
R0
Bus controller
Figure 3.1.1 S1C17 Configuration
Seiko Epson Corporation
Special registers
Program counter
Bit 0 Bit 23
PC
Stack pointer
Bit 23
SP
Processor status register
Bit 7 Bit 0
PSR
IL[2:0] (Bits [7:5]): Interrupt Level
IE (Bit 4): Interrupt Enable
C (Bit 3): Carry
V (Bit 2): Overflow
Z (Bit 1): Zero
N (Bit 0): Negative
Debugger
3 CPU AND DEBUGGER
Bit 0
Bit 0
DCLK
DSIO
DST2
3-1