Epson S1C17M20 Technical Manual page 5

3.3.4 External Connection ......................................................................................... 3-3
3.3.5 Flash Security Function .................................................................................... 3-3
3.4 Control Register .............................................................................................................. 3-4
MISC PSR Register ................................................................................................................... 3-4
Debug RAM Base Register ....................................................................................................... 3-4
4 Memory and Bus ..........................................................................................................4-1
4.1 Overview ......................................................................................................................... 4-1
4.2 Bus Access Cycle ........................................................................................................... 4-1
4.3 Flash Memory ................................................................................................................. 4-2
4.3.1 Flash Memory Pin ............................................................................................. 4-2
4.3.2 Flash Bus Access Cycle Setting ....................................................................... 4-2
4.3.3 Flash Programming ........................................................................................... 4-3
4.4 RAM ................................................................................................................................ 4-3
4.5 Peripheral Circuit Control Registers ................................................................................ 4-3
4.5.1 System-Protect Function .................................................................................. 4-8
4.6 Control Registers ............................................................................................................ 4-8
MISC System Protect Register ................................................................................................. 4-8
MISC IRAM Size Register.......................................................................................................... 4-8
FLASHC Flash Read Cycle Register ......................................................................................... 4-8
5 Interrupt Controller (ITC) .............................................................................................5-1
5.1 Overview ......................................................................................................................... 5-1
5.2 Vector Table .................................................................................................................... 5-1
5.2.1 Vector Table Base Address (TTBR) ................................................................... 5-3
5.3 Initialization ..................................................................................................................... 5-3
5.4 Maskable Interrupt Control and Operations ................................................................... 5-3
5.4.1 Peripheral Circuit Interrupt Control ................................................................... 5-3
5.4.2 ITC Interrupt Request Processing .................................................................... 5-4
5.4.3 Conditions to Accept Interrupt Requests by the CPU...................................... 5-4
5.5 NMI .................................................................................................................................. 5-4
5.6 Software Interrupts ......................................................................................................... 5-4
5.7 Interrupt Processing by the CPU .................................................................................... 5-5
5.8 Control Registers ............................................................................................................ 5-5
MISC Vector Table Address Low Register ................................................................................ 5-5
MISC Vector Table Address High Register ................................................................................ 5-5
ITC Interrupt Level Setup Register x ......................................................................................... 5-5
6 I/O Ports (PPORT) .........................................................................................................6-1
6.1 Overview ......................................................................................................................... 6-1
6.2 I/O Cell Structure and Functions ..................................................................................... 6-2
6.2.1 Schmitt Input .................................................................................................... 6-3
6.2.2 Over Voltage Tolerant Fail-Safe Type I/O Cell ................................................... 6-3
6.2.3 Pull-Up/Pull-Down ............................................................................................ 6-3
6.2.4 CMOS Output and High Impedance State ....................................................... 6-3
6.3 Clock Settings ................................................................................................................. 6-3
6.3.1 PPORT Operating Clock ................................................................................... 6-3
6.3.2 Clock Supply in SLEEP Mode .......................................................................... 6-4
6.3.3 Clock Supply in DEBUG Mode ......................................................................... 6-4
6.4 Operations ...................................................................................................................... 6-4
6.4.1 Initialization ....................................................................................................... 6-4
6.4.2 Port Input/Output Control ................................................................................. 6-5
6.5 Interrupts ......................................................................................................................... 6-6
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Seiko Epson Corporation
CONTENTS
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