P Port Interrupt Flag Group Register - Epson S1C17M20 Technical Manual

PCLK.CLKDIV[3:0] bits
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.

P Port Interrupt Flag Group Register

Register name Bit
PINTFGRP 15–13 –
12
11
10
9
8
7
6
5
4
3
2
1
0
*1: Only the bits corresponding to the port groups that support interrupts are provided.
Bits 15–13 Reserved
Bits 12–0 PxINT
These bits indicate that Px port group includes a port that has generated an interrupt.
1 (R): A port generated an interrupt
0 (R): No port generated an interrupt
The PINTFGRP.PxINT bit is cleared when the interrupt flag for the port that has generated an interrupt
is cleared.
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Table 6.6.3 Clock Source and Division Ratio Settings
0x0
IOSC
Bit name Initial
0x0
PcINT 0
PbINT 0
PaINT 0
P9INT 0
P8INT 0
P7INT 0
P6INT 0
P5INT 0
P4INT 0
P3INT 0
P2INT 0
P1INT 0
P0INT 0
Seiko Epson Corporation
PCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/32,768
1/16,384
1/8,192
1/4,096
1/2,048
1/1,024
1/512
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
1/1
Reset R/W
– R –
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
H0 R
6 I/O PORTS (PPORT)
0x3
EXOSC
1/1
Remarks
6-11