Uart3 Ch.n Mode Register - Epson S1C17M20 Technical Manual

12 UART (UART3)
Bits 1–0 CLKSRC[1:0]
These bits select the clock source of the UART3.
UAnCLK.
CLKDIV[1:0] bits
0x3
0x2
0x1
0x0
(Note) The oscillation circuits/external input that are not supported in this IC cannot be
selected as the clock source.
Note: The UAnCLK register settings can be altered only when the UAnCTL.MODEN bit = 0.

UART3 Ch.n Mode Register

Register name Bit
UAnMOD 15–13 –
12
11
10
9
8
7
6
5
4
3
2
1
0
Bits 15–13 Reserved
Bit 12 PECAR
This bit selects the carrier modulation period.
1 (R/W): Carrier modulation during H data period
0 (R/W): Carrier modulation during L data period
Bit 11 CAREN
This bit enables the carrier modulation function.
1 (R/W): Enable carrier modulation function
0 (R/W): Disable carrier modulation function
Bit 10 BRDIV
This bit sets the UART3 operating clock division ratio for generating the transfer (sampling) clock
using the baud rate generator.
1 (R/W): 1/4
0 (R/W): 1/16
Bit 9 INVRX
This bit enables the USINn input inverting function.
1 (R/W): Enable input inverting function
0 (R/W): Disable input inverting function
Bit 8 INVTX
This bit enables the USOUTn output inverting function.
1 (R/W): Enable output inverting function
0 (R/W): Disable output inverting function
Bit 7 Reserved
12-10
Table 12.8.1 Clock Source and Division Ratio Settings
0x0
IOSC
1/8
1/4
1/2
1/1
Bit name Initial
0x0
PECAR 0
CAREN 0
BRDIV 0
INVRX 0
INVTX 0
– 0
PUEN 0
OUTMD 0
IRMD 0
CHLN 0
PREN 0
PRMD 0
STPB 0
Seiko Epson Corporation
UAnCLK.CLKSRC[1:0] bits
0x1 0x2
OSC1 OSC3
1/1 1/8
1/4
1/2
1/1
Reset R/W
– R –
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
– R
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
H0 R/W
0x3
EXOSC
1/1
Remarks
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)