Epson S1C17M20 Technical Manual page 36

SLEEP mode
When the CPU executes the slp instruction, it suspends program execution and stops operating. This state is
SLEEP mode. In this mode, the clock sources stop operating as well. However, the clock source in which the
CLGOSC.IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit is set to 0 keeps operating, so the peripheral
circuits with the clock being supplied can also operate. By setting this mode when no software processing and
peripheral circuit operations are required, power consumption can be less than HALT mode.
Note: The current consumption when a clock source is active in SLEEP mode by setting the CLGOSC.
IOSCSLPC/OSC1SLPC/OSC3SLPC/EXOSCSLPC bit to 0 is equivalent to the value in HALT
mode with the same clock source condition (refer to "Current Consumption, Current consump-
tion in HALT mode I
DEBUG mode
When a debug interrupt occurs, the CPU enters DEBUG mode. DEBUG mode is canceled when the retd in-
struction is executed. For more information on DEBUG mode, refer to "Debugger" in the "CPU and Debugger"
chapter.
Transition takes place automatically by the
initial boot sequence after a request from
the reset source is canceled.
OSC1
HALT
OSC1
RUN
Figure 2.4.2.1 Operating Mode-to-Mode State Transition Diagram
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
, I , and I
HALT1 HALT2 HALT3
RESET
(Initial state)
IOSC
RUN
CLGSCLK.CLKSRC[1:0] = 0x3
OSC3
RUN
OSC3
HALT
Seiko Epson Corporation
2 POWER SUPPLY, RESET, AND CLOCKS
" in the "Electrical Characteristics" chapter).
IOSC
HALT
CLGSCLK.CLKSRC[1:0] = 0x1
∗ In RUN and HALT modes, the clock sources not used
as SYSCLK can be all disabled.
slp instruction
RUN
HALT/SLEEP
cancelation signal
(wake-up)
Debug interrupt
RUN/
HALT/ DEBUG
SLEEP
retd instruction
EXOSC
RUN
EXOSC
HALT
SLEEP
2-13