Epson S1C17M20 Technical Manual page 57

Table 4.6.2 Setting Number of Bus Access Cycles for Flash Read
FLASHCWAIT.RDWAIT[1:0] bits Number of bus Access cycles
Note: Be sure to set the FLASHCWAIT.RDWAIT[1:0] bits before the system clock is configured.
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
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0x2
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Seiko Epson Corporation
System clock frequency
4 21.0 MHz (max.)
3 18.9 MHz (max.)
2 12.6 MHz (max.)
1 6.3 MHz (max.)
4 MEMORY AND BUS
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