Overview; Features - Epson S1C17M20 Technical Manual

1 Overview

The S1C17M20/M21/M22/M23/M24/M25 is a 16-bit embedded Flash MCU that features low power consump-
tion. The embedded Flash memory can also be used as an EEPROM emulation data memory via software. The
S1C17M20/M21/M22/M23/M24/M25 includes various serial interfaces, an A/D converter, and various timers as
well as a high-performance 16-bit CPU. It is suitable for applications that require an A/D conversion function, such
as household equipment and FA products.

1.1 Features

Model
CPU
CPU core
Other
Embedded Flash memory
Capacity
(for both instructions and data)
Erase/program count
Other
Embedded RAM
Capacity
Clock generator (CLG)
System clock source
System clock frequency
(operating frequency)
IOSC oscillator circuit
(boot clock source)
OSC1 oscillator circuit
OSC3 oscillator circuit
EXOSC clock input
Other
I/O port (PPORT)
Number of general- I/O port
purpose ports Output port
Other
Number of input interrupt ports
Number of ports that support
universal port multiplexer (UPMUX)
Timers
Watchdog timer (WDT2)
Real-time clock (RTCA)
16-bit timer (T16)
16-bit PWM timer (T16B)
Supply voltage detector (SVD3)
Detection voltage
Detection level
Other
S1C17M20/M21/M22/M23/M24/M25
TECHNICAL MANUAL (Rev. 1.0)
Table 1.1.1 Features
S1C17M20/M23
24-pin PKG 32-pin PKG
Seiko Epson original 16-bit RISC CPU core S1C17
On-chip debugger
16K bytes (S1C17M20/M21/M22)
32K bytes (S1C17M23/M24/M25)
1,000 times (min.) * Programming by the debugging tool ICDmini
Security function to protect from reading/programming by ICDmini
On-board programming function using ICDmini
Flash programming voltage can be generated internally.
2K bytes
4 sources (IOSC/OSC1/OSC3/EXOSC)
21 MHz (max.)
700 kHz (typ.) embedded oscillator
23 µs (max.) starting time (time from cancelation of SLEEP state to vector table read by the CPU)
– 32.768 kHz (typ.) crystal oscillator
32 kHz (typ.) embedded oscillator
– Oscillation stop detection circuit included
– 21 MHz (max.) crystal/ceramic oscillator
12, 16, and 20 MHz-switchable embedded oscillator
– Auto-trimming function for the embedded oscillator
21 MHz (max.) square or sine wave input
Configurable system clock division ratio
Configurable system clock used at wake up from SLEEP state
Operating clock frequency for the CPU and all peripheral circuits is selectable.
17 bits (max.) 23 bits (max.)
1 bit (max.)
Pins are shared with the peripheral I/O.
15 bits (max.) 19 bits (max.)
15 bits 19 bits
A peripheral circuit I/O function selected via software can be assigned to each port.
Generates NMI or watchdog timer reset.
Programmable NMI/reset generation cycle
128–1 Hz counter, second/minute/hour/day/day of the week/month/year counters
Theoretical regulation function for 1-second correction
Alarm and stopwatch functions
4 channels
Generates the SPIA master clocks and the ADC12A trigger signal.
2 channels
Event counter/capture function
PWM waveform generation function
Number of PWM output or capture input ports: 2 ports/channel
V or external voltage (one external voltage input port is provided and an external voltage level
DD
can be detected even if it exceeds V
V : 28 levels (1.8 to 5.0 V)/external voltage: 32 levels (1.2 to 5.0 V)
DD
Intermittent operation mode
Generates an interrupt or reset according to the detection level evaluation.
Seiko Epson Corporation
S1C17M21/M24
39 bits (max.)
35 bits (max.)
32 bits
.)
DD
1 OVERVIEW
S1C17M22/M25
1-1