40 Mhz Bandwidth I.f. System Block Diagram - Keysight n9020a Service Manual

40 MHz BW IF SYSTEM BLOCK DIAGRAM
A2 ANALOG IF
12 MHz
322.5 MHz 1 dB
J100
IN
W37 Step
From
A15J900
+13 dB
25 MHz
300 kHz
IF COMB CAL
HI/
LO
THERMOMETER
22.5 MHz
COMB
J820 J300
P/O
W2
ribbon cable
W14
From A16J711
FOOTNOTES
(1) Analyzers without any of the following options: B85, B1A, B1X
(2) Analyzers with any of the following options: B85, B1A, B1X
(3) W42 is used on serial prefix < MY/SG/US5233 ;
W54 is used on serial prefix > MY/SG/US5233 and all analyzers with Option B85, B1A, or B1X
(4) This cable only used on analyzers with serial prefix < MY/SG/US5233
without any of the following options;: B85, B1A, B1X
(5) Connection depends upon option and serial prefix.
Serial Prefix Option Cable
<MY/SG/US5233 B40, DP2, or MPB W40
any B85, B1A, B1X W55
>MY/SG/US5233 B40, DP2, or MPB W50
blockm40_if40
W38
From A15J901
From A25J102
W52
300 kHz/800 kHz
LC
25 MHz
+13 dB
22.5 MHz
22.5 MHz
to mux
to mux
12 MHz
XTAL
9 kHz/60 kHz
BURST CARRIER TRIGGER
TRIG
TRIG
+
-
To mux
GAIN
LEVEL
300 MHz LO
+10 dBm
From A16J706
From A15J716
From A15J705
A3 DIGITAL IF
4
1
W43
WB_ALIGN_DATA
J18
40 MHz BW
ST GT
250 MHz CF
2
J15
250 MHz
IF
DITHER
STEP
GAIN 22.5 MHz
W41
+4 dBm J19
22.5 MHz
J601
IF
Lockn
100 MHz
REF J14
J820
DAC
P/O
W43
ribbon cable J10
TRIGGER 1 IN
(BNC)
J9
TRIGGER 2 IN
(BNC)
3
W42
3
W54
P/O W2 Ribbon Cable
STEP
CAL
FELDSPAR
ADC2
ADC2
DRIVE DSP
clock
(12 bit)
ADC2
Clk
ADC1 T2 Rx
Clk Module
ADC1 ADC1
(16 bit)
200 MHz 200 MHz
X2
ADC2p/n_CLK
Diag_to_adc 200 MHz
Notch
AFPGA_100MHz
INTERPOLATOR
INTERP_CAL_TRIG
CAL TRIGGER
ANALOG FPGA
EXT_TRIG_1
GATE_ARM
DAC
Trig1_Lev GATE_TRIG
SWEEP_ARM
EXT_TRIG_2
SWEEP_TRIG
DAC
Trig2_Lev
SETTLED
TRIG_1
TRIG_2
LINE_TRIG
COMB_1
INT_SWP
SETTLED
AIF_TRIG
COMB_2
ASG/COMB GEN
EXT SYNC
TRIG_OUT1
TRIGGER TRIG_OUT2
BUFFER INT_SWP
J20
5
W55
To A25J805
5
W40
ECAL IN
To A13J6
5
W50
From A15J926
ALIGN OUT J17
N.C.
J16
PECL -> ECL FELDSPAR_CLK
Noise Source
J11
Drive +28V
Noise
(BNC)
125 MHz
Source
SNS
Noise Source
Memory Capture
Controller Memory
J4
Digital Bus
Recon (15.0)
RECONSTRUCTION
CA6/AUDIO
(P1-C6)
Analog Out
Recon
(BNC)
Gain DAC
J5
ADC1 Clk
6 dB
Clock
SYS Clk
Distribution
FELDSPAR Clk
IF 10M REF
10MHz
OUT
J13
(BNC)
AFPGA_10 MHz
AFPGA_100 MHz
T2
(TRIGGER MODULE)
TEMPERATURE
SENSOR
J7
TRIGGER1
T2
OUT
TRIG_OUT1 ILB Module
(BNC)
TRIG_OUT2
INT_SWP
TRIGGER2
TSTRETCH PART_SAMP J6
OUT
(BNC)
PULSE
STRETCHER ILB Bus PCI Bus
J8
SYNC
(BNC)
40 MHz BW IF SYSTEM
BLOCK DIAGRAM