System Synchronization Clocks (Pxi_Clk10, Pxie_Clk100, Pxie_Sync100); 10 Mhz System Reference Clock: Pxi_Clk10; 100 Mhz System Reference Clock: Pxie_Clk100 And Pxie_Sync100 - Keysight M9005A User Manual

Specifications
System Synchronization Clocks
(PXI_CLK10, PXIe_CLK100, PXIe_SYNC100)

10 MHz System Reference Clock: PXI_CLK10

- Maximum slot-to-slot skew
- Accuracy
- Maximum jitter
- Duty-factor
- Unloaded signal swing

100 MHz System Reference Clock: PXIe_CLK100 and PXIe_SYNC100

- Maximum slot-to-slot skew
- Accuracy
- Maximum jitter
- Duty-factor for PXIe_CLK100
44
250 ps
±25 ppm max. (guaranteed over the operating temperature range)
The 10 MHz system reference clock does not require calibration.
5 ps RMS phase-jitter (10 Hz–1 MHz range)
45%–55%
3.3 V ±0.3 V
For other specifications refer to the PXI-1 Hardware Specification.
100 ps
±25 ppm max. (guaranteed over the operating temperature range)
3 ps RMS phase-jitter (10 Hz–12 kHz range) 2 ps RMS phase-jitter (12 kHz–
20 MHz range)
45%–55%
M9005A Specifications
Keysight M9005A PXIe Chassis User Guide